diff options
authorDennis Peeten <>2008-05-19 18:55:30 (GMT)
committerDennis Peeten <>2008-05-19 18:55:30 (GMT)
commit4d4cfd286c94fdfc7d38e527020fe06dc9426598 (patch)
parent17d5164dde1ea28490e7266a40308dfe89391b68 (diff)
sorry, forgot the bib file
1 files changed, 65 insertions, 0 deletions
diff --git a/report/references.bib b/report/references.bib
new file mode 100644
index 0000000..97c6891
--- /dev/null
+++ b/report/references.bib
@@ -0,0 +1,65 @@
+title={Use of preferred preemption points in cache-based real-time systems },
+author={Simonson, J. and Patel, J.H.},
+journal={Computer Performance and Dependability Symposium, 1995. Proceedings., International},
+year={24-26 Apr 1995},
+keywords={ cache storage, computational complexity, performance evaluation, real-time systems cache memory arrangements, cache-based real-time systems, complexity, preemptable multi-tasking environment, preferred preemption points, system timing constraints, tight upper bounds, time-critical applications, timing effects, worst-case execution times},
+ISSN={}, }
+ author = {Giorgio C. Buttazzo},
+ title = {Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications, Second edition (Real-Time Systems Series)},
+ year = {2005},
+ isbn = {978-0-387-23137-2},
+ publisher = {Springer-Verlag TELOS},
+ address = {Santa Clara, CA, USA},
+ }
+ author = {Sheayun Lee and Chang-Gun Lee and Minsuk Lee and Sang Lyul Min and Chong-Sang Kim},
+ title = {Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems},
+ booktitle = {LCTES '98: Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems},
+ year = {1998},
+ isbn = {3-540-65075-X},
+ pages = {51--64},
+ publisher = {Springer-Verlag},
+ address = {London, UK},
+ }
+title={Integrating the timing analysis of pipelining and instruction caching},
+author={Healy, C.A. and Whalley, D.B. and Harmon, M.G.},
+journal={Real-Time Systems Symposium, 1995. Proceedings., 16th IEEE},
+year={5-7 Dec 1995},
+keywords={buffer storage, delays, graphical user interfaces, pipeline processing, real-time systems, timingcode segments, data memory references, delays, execution time, graphical user interface, instruction caching, memory references, multicycle delays, pipeline path analysis, pipelining, real-time systems, timing analysis, timing analyzer, worst-case performance},
+ISSN={}, }
+ author = {P. Gai, L. Abeni and G. Buttazzo},
+ title = {Multiprocessor DSP scheduling in system-on-a-chip architectures},
+ booktitle = {ECRTS'02: 14th Euromicro Conference on Real-Time Systems},
+ year = {2002},
+ isbn = {0-7695-1665-3},
+ pages = {231--238},
+ publisher = {IEEE},
+title={Cooperative scheduling of multiple resources},
+author={Saewong, S. and Rajkumar, R.},
+journal={Real-Time Systems Symposium, 1999. Proceedings. The 20th IEEE},
+keywords={computational complexity, delays, performance evaluation, processor scheduling, timingNP-complete problem, conjuctive admission control, cooperative scheduling, disk bandwidth, distributed real-time system, end-to-end delays, host processor, multiple resources, network bandwidth, protocol services, resource decoupling, timing constraints},
+ISSN={}, }