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diff --git a/report/chapter6.tex b/report/chapter6.tex index 5921ea0..ac0cc4c 100644 --- a/report/chapter6.tex +++ b/report/chapter6.tex @@ -1,36 +1,2 @@ -%\section{Literature}
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-%\small
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-%\begin{tabbing}
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-%\textbf{[1]} \= Jonathan Simonson, Janak H. Patel. Use of preferred preemption points in cache-based \\
-%\> real-time systems. IEEE Computer Society Washington, DC, USA 1995 \\
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-%\textbf{[2]} \= Healy, C.A., Whalley, D.B., Harmon, M.G. Integrating the Timing Analysis of Pipelining \\
-%\> and Instruction Caching. Dept. of Comput. Sci., Florida State Univ., Tallahassee, FL 1995 \\
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-%\textbf{[3]} \= Giorgio C. Buttazzo. Hard Real-Time Computing Systems, 2nd Revised edition \\
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-%\textbf{[4]} \= Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong Sang Kim. Limited \\
-%\> preemptible scheduling to embrace cache memory in real-time systems. Dept. of Computer \\
-%\> Engineering, Seoul National University and Hansung University Seoul, Korea 1998 \\
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-%\\
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-%\textbf{[5]} \= Jonathan Simonson, Janak H. Patel. Use of preferred preemption points in cache-based \\
-%\> real-time systems. IEEE Computer Society Washington, DC, USA 1995 \\
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-%\end{tabbing}
-
\bibliographystyle{alpha}
-\bibliography{references}
\ No newline at end of file +\bibliography{references}
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