From 17d5164dde1ea28490e7266a40308dfe89391b68 Mon Sep 17 00:00:00 2001
From: Wilrik de Loose <wilrik@wilrik.nl>
Date: Mon, 19 May 2008 09:48:57 +0000
Subject: Chapter 3 + image

---
 report/chapter3.tex                          |   8 ++++----
 report/figs/shared_memory_multiprocessor.png | Bin 0 -> 33543 bytes
 2 files changed, 4 insertions(+), 4 deletions(-)
 create mode 100644 report/figs/shared_memory_multiprocessor.png

diff --git a/report/chapter3.tex b/report/chapter3.tex
index 22d0dd9..265e44e 100644
--- a/report/chapter3.tex
+++ b/report/chapter3.tex
@@ -27,7 +27,7 @@ In \cite{hwh-itapic-95} a method to determine the worst case execution times was
 In any multiprocessing system cooperating processes share data via shared data objects. A typical abstraction of a shared memory multiprocessor real-time system configuration is depicted in figure 1. Each node of the system contains a processor together with its local memory. All nodes are connected to the shared memory via an interconnection network.
 
 \begin {center}
-  %\includegraphics[width=80mm]{shared_memory_multiprocessor.png} \\
+  \includegraphics[width=80mm]{figs/shared_memory_multiprocessor.png} \\
   Figure 1. Shared memory multiprocessor system structure
 \end {center}
 
@@ -57,7 +57,7 @@ In order to apply this to the GPP + DSP multiprocessor architecture, Gai et. al.
 	\caption{Structure of a DSP task}
 \end{figure}
 
-When executing a DSP task, a hole within each job is generated in the schedule of the master processor. Gai et. al. show that the earliest deadline first (EDF) and rate monotonic (RM) scheduling algorithms do not always yield a feasible schedule, while one exists. Figure \ref{fig:infeasible} shows an infeasible task set when scheduled by RM or EDF. Figure \ref{fig:feasible} shows the same task set scheduled using a fixed priority assignment where $ \tau_2 \prec \tau_1 $, such that $ \tau_2 $ executes in the holes of the master CPU's schedule. 
+When executing a DSP task, a hole within each job is generated in the schedule of the master processor. Gai et. al. show that the earliest deadline first (EDF) and rate monotonic (RM) scheduling algorithms do not always yield a feasible schedule, while one exists. Figure \ref{fig:infeasible} shows an infeasible task set when scheduled by RM or EDF. Figure \ref{fig:feasible} shows the same task set scheduled using a fixed priority assignment where $ \tau_2 \prec \tau_1 $, such that $ \tau_2 $ executes in the holes of the master CPU's schedule.
 
 \begin{figure}[ht]
 	\includegraphics{figs/infeasible.pdf}
@@ -71,7 +71,7 @@ When executing a DSP task, a hole within each job is generated in the schedule o
 	\caption{A feasible schedule with fixed priority assignment  $ \tau_2 \prec \tau_1 $.}
 \end{figure}
 
-The main idea is to modify the scheduler to exploit these holes to schedule some other task on the master processor to improve the schedulability bound of the system. This is achieved by modeling the DSP request of a task $ \tau_i $ as a remote procedure call that blocks $ \tau_i $ for $ B_i $ units of time, waiting for its completion. The scheduling algorithm uses a fixed priority assignment. In order to determine the next task to be executed, the scheduler enqueues regular tasks and DSP tasks in two separate queues that are ordered by priority, as shown in Figure \ref{fig:dspscheduler}. 
+The main idea is to modify the scheduler to exploit these holes to schedule some other task on the master processor to improve the schedulability bound of the system. This is achieved by modeling the DSP request of a task $ \tau_i $ as a remote procedure call that blocks $ \tau_i $ for $ B_i $ units of time, waiting for its completion. The scheduling algorithm uses a fixed priority assignment. In order to determine the next task to be executed, the scheduler enqueues regular tasks and DSP tasks in two separate queues that are ordered by priority, as shown in Figure \ref{fig:dspscheduler}.
 
 \begin{figure}[ht]
 	\includegraphics{figs/dspscheduler.pdf}
@@ -81,6 +81,6 @@ The main idea is to modify the scheduler to exploit these holes to schedule some
 
 When the DSP is idle the scheduler selects the task with the highest priority between those at the head of the two queues. When the DSP is active, the scheduler select the highest priority task from the head of the regular queue only. In this way, a task using the DSP blocks all other tasks requiring the DSP, but not the regular tasks, which can freely execute on the master processor in the holes created by DSP activities.
 
-Because the DSP tasks executing on the DSP cannot be preempted, it can happen that a lower priority DSP task $ \tau_i $ is blocking a higher priority task that was released during the execution of $ \tau_i $ on the DSP. The blocking of high priority DSP tasks by lower priority DSP task has to be accounted for in the schedulability test. This test is presented {gab-mdssa-02} using the hyperbolic bound. 
+Because the DSP tasks executing on the DSP cannot be preempted, it can happen that a lower priority DSP task $ \tau_i $ is blocking a higher priority task that was released during the execution of $ \tau_i $ on the DSP. The blocking of high priority DSP tasks by lower priority DSP task has to be accounted for in the schedulability test. This test is presented {gab-mdssa-02} using the hyperbolic bound.
 
 The article furthermore present results of a simulation of the described algorithm and compares them to schedules generated by the distributed priority ceiling protocol (DPCP). However they do not mention the method of priority assignment used in their simulation.
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