Architecture specific stuff, basically, without drivers.

44 files changed, 2211 insertions, 8 deletions

diff --git a/uClinux-2.4.20-uc1/arch/armnommu/Makefile b/uClinux-2.4.20-uc1/arch/armnommu/Makefile
index bafd221..92a7757 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/Makefile
+++ b/uClinux-2.4.20-uc1/arch/armnommu/Makefile
@@ -20,6 +20,14 @@ ifeq ($(CONFIG_DEBUG_INFO),y)
 CFLAGS		+=-g
 endif
 
+ifeq ($(CONFIG_WINBOND_EVB),y)
+CFLAGS		+=-D__WB_EVB__
+endif
+
+ifeq ($(CONFIG_WINBOND_PTB),y)
+CFLAGS		+=-D__WB_POSTAX__
+endif
+
 CFLAGS += -DNO_MM
 AFLAGS += -DNO_MM
 
@@ -54,8 +62,8 @@ LINKFLAGS	+= -EB
 LDFLAGS		+= -EB
 endif
 
-CFLAGS		+= $(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float
-AFLAGS		+= $(apcs-y) $(proc-y) -msoft-float -mno-fpu
+CFLAGS		+= $(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes
+AFLAGS		+= $(apcs-y) $(proc-y) -mno-fpu
 
 LIBGCC		:= $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)
 
@@ -185,6 +193,11 @@ TEXTADDR   	 = 0x00008000
 MACHINE    	 = snds100
 endif
 
+ifeq ($(CONFIG_BOARD_W90N745),y)
+TEXTADDR   	 = 0x00008000
+MACHINE    	 = W90N745
+endif
+
 ifeq ($(CONFIG_BOARD_EVS3C4530HEI),y)
 TEXTADDR         = 0x00020000
 MACHINE          = evS3C4530HEI
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/boot/Makefile b/uClinux-2.4.20-uc1/arch/armnommu/boot/Makefile
index b202695..dd1fe5e 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/boot/Makefile
+++ b/uClinux-2.4.20-uc1/arch/armnommu/boot/Makefile
@@ -113,6 +113,11 @@ ZRELADDR	 = 0x00008000
 ZTEXTADDR	 = 0x00000000
 endif
 
+ifeq ($(CONFIG_BOARD_W90N745),y)
+ZRELADDR	 = 0x00008000
+ZTEXTADDR	 = 0x00000000
+endif
+
 #
 # If you don't define ZRELADDR above,
 # then it defaults to ZTEXTADDR
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/boot/compressed/head.S b/uClinux-2.4.20-uc1/arch/armnommu/boot/compressed/head.S
index e70906e..0a90491 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/boot/compressed/head.S
+++ b/uClinux-2.4.20-uc1/arch/armnommu/boot/compressed/head.S
@@ -10,7 +10,7 @@
 #include <linux/config.h>
 #include <linux/linkage.h>
 
-#ifdef CONFIG_BOARD_SNDS100
+#if defined(CONFIG_BOARD_SNDS100) || defined(CONFIG_BOARD_W90N745)
 #include <asm/hardware.h>
 #endif
 
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/config.in b/uClinux-2.4.20-uc1/arch/armnommu/config.in
index 6decbd7..06b3690 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/config.in
+++ b/uClinux-2.4.20-uc1/arch/armnommu/config.in
@@ -15,6 +15,12 @@ define_bool MAGIC_ROM_PTR y
 # End uclinux additions -------------------------------------------------------
 
 
+mainmenu_option next_comment
+comment 'Target board selection'
+choice 'is selected as target board' \
+	"EV_BOARD         CONFIG_WINBOND_EVB\
+	POS-TAX_DEMO_BOARD        CONFIG_WINBOND_PTB" EV_BOARD
+endmenu
 #------------------------------------------------------------------------------
 #                         C o d e    m a t u r i t y
 #------------------------------------------------------------------------------
@@ -47,7 +53,8 @@ choice 'ARM system type'	\
 	  Triscend-A7S		CONFIG_ARCH_TA7S \
 	  SWARM			CONFIG_ARCH_SWARM \
 	  Samsung		CONFIG_ARCH_SAMSUNG \
-	  Atmel			CONFIG_ARCH_ATMEL" TI-DSC21
+	  Atmel			CONFIG_ARCH_ATMEL \
+	  Winbond		CONFIG_ARCH_WINBOND" TI-DSC21
 
 bool 'Generate big endian code' CONFIG_CPU_BIG_ENDIAN
 
@@ -172,6 +179,34 @@ if [ "$CONFIG_ARCH_ATMEL" = "y" ]; then
    fi
 fi
 
+if [ "$CONFIG_ARCH_WINBOND" = "y" ]; then
+choice 'Board Implementation' \
+    "WINBOND-W90N745 CONFIG_BOARD_W90N745" WINBOND-W90N745
+
+    if [ "$CONFIG_BOARD_W90N745" = "y" ]; then
+    define_string CONFIG_SPU_NAME "W90N745"
+    define_bool CONFIG_CPU_W90N745      y
+    define_bool CONFIG_CPU_ARM710       y
+    define_bool CONFIG_CPU_32v4         y
+    define_bool CONFIG_CPU_32           y
+    define_bool CONFIG_CPU_26           n
+    define_bool CONFIG_NO_PGT_CACHE     y
+    define_bool CONFIG_CPU_WITH_CACHE   y
+    define_bool CONFIG_CPU_WITH_MCR_INSTRUCTION n
+    define_int  CONFIG_ARM_CLK          80000000
+    define_bool CONFIG_SERIAL_W90N745   y
+    if [ "$CONFIG_SET_MEM_PARAM" = "n" ]; then
+       define_hex DRAM_BASE 0x00000000
+       define_hex DRAM_SIZE 0x00800000
+       define_hex FLASH_MEM_BASE 0xFF000000
+       define_hex FLASH_SIZE 0x00200000
+    fi
+
+    hex 'ROMFS Base Address ' ROMFS_BASE 0x00700000
+  fi
+
+fi
+
 if [ "$CONFIG_ARCH_NETARM" = "y" ]; then
    define_bool CONFIG_CPU_ARM710 y
    define_bool CONFIG_CPU_ARM7TDMI y
@@ -450,6 +485,22 @@ source drivers/char/Config.in
 source drivers/usb/Config.in
 source drivers/ieee1394/Config.in
 source drivers/message/i2o/Config.in
+
+if [ "$CONFIG_BOARD_W90N745" = "y" ]; then
+source drivers/gpio/Config.in
+fi
+
+#------------------------------------------------------------------------------
+#                         S o u n d    D e v i c e s
+#------------------------------------------------------------------------------
+mainmenu_option next_comment
+comment 'Sound support'
+tristate 'Sound support?' CONFIG_SOUND
+if [ "$CONFIG_SOUND" != "n" ]; then
+   source drivers/sound/Config.in
+fi
+endmenu
+
 #------------------------------------------------------------------------------
 #                     K e r n e l    H a c k i n g
 #------------------------------------------------------------------------------
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/kernel/calls.S b/uClinux-2.4.20-uc1/arch/armnommu/kernel/calls.S
index ee1b74a..c769133 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/kernel/calls.S
+++ b/uClinux-2.4.20-uc1/arch/armnommu/kernel/calls.S
@@ -236,6 +236,22 @@ __syscall_start:
 		.long	SYMBOL_NAME(sys_mincore)
 /* 220 */	.long	SYMBOL_NAME(sys_madvise)
 		.long	SYMBOL_NAME(sys_fcntl64)
+		.long	SYMBOL_NAME(sys_FindImage)
+		.long	SYMBOL_NAME(sys_DelImage)
+		.long	SYMBOL_NAME(sys_CorruptCheck)
+/* 225 */	.long	SYMBOL_NAME(sys_ReadWinbondFlash)
+		.long	SYMBOL_NAME(sys_WriteWinbondFlash)
+		.long	SYMBOL_NAME(sys_WinbondFlashBlockSize)
+		.long	SYMBOL_NAME(sys_WinbondFlashTotalSize)
+		.long	SYMBOL_NAME(sys_WinbondFlashBase)
+
+#ifdef CONFIG_USB_WBUSBD
+/* 230 */	
+		.long   SYMBOL_NAME(sys_WinbondUSBRead)
+		.long   SYMBOL_NAME(sys_WinbondUSBWrite)
+		.long   SYMBOL_NAME(sys_WinbondUSBGetCBW)
+#endif
+		
 __syscall_end:
 
 		.rept	NR_syscalls - (__syscall_end - __syscall_start) / 4
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/kernel/entry-armv.S b/uClinux-2.4.20-uc1/arch/armnommu/kernel/entry-armv.S
index b7d1bd5..776792e 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/kernel/entry-armv.S
+++ b/uClinux-2.4.20-uc1/arch/armnommu/kernel/entry-armv.S
@@ -777,6 +777,21 @@ irq_prio_netarm:
 		.macro irq_prio_table
 		.endm
 
+#elif defined(CONFIG_CPU_W90N745)
+
+		.macro disable_fiq
+		.endm
+
+		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+		ldr	\base, =AIC_IPER
+		ldr	\irqnr, [\base]
+		@mov	\irqnr, \irqnr, lsr #2
+		teq	\irqnr, #0x0
+		.endm
+
+		.macro irq_prio_table
+		.endm
+
 #elif defined(CONFIG_CPU_S3C3410)
 
 		.macro disable_fiq
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/kernel/head-armv.S b/uClinux-2.4.20-uc1/arch/armnommu/kernel/head-armv.S
index b297678..31a91f0 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/kernel/head-armv.S
+++ b/uClinux-2.4.20-uc1/arch/armnommu/kernel/head-armv.S
@@ -143,6 +143,8 @@ __entry:
 		mov	r1, #MACH_TYPE_SNDS100
 #elif defined (CONFIG_BOARD_SMDK40100)
 		mov	r1, #MACH_TYPE_S3C3410
+#elif defined (CONFIG_BOARD_W90N745)
+		mov	r1, #MACH_TYPE_W90N745
 #endif
 
 		mov	r0, #F_BIT | I_BIT | MODE_SVC	@ make sure svc mode
@@ -199,6 +201,42 @@ LC0:	.long	__bss_start
         .long	init_task_union+8192
 #endif
 
+#if defined(CONFIG_BOARD_W90N745)
+
+        adr	r5, LC0
+        ldmia	r5, {r5, r6, r8, r9, sp}			@ Setup stack
+
+        /*  Copy data sections to their new home.  */
+
+
+        /*  Clear BSS */
+        mov	r4, #0
+1:      cmp	r5, r8					
+        strcc	r4, [r5],#4
+        bcc	1b
+
+        /*  Pretend we know what our processor code is (for arm_id)   */
+
+	ldr	r2, W90N745_PROCESSOR_TYPE
+
+	str     r2, [r6]
+	mov     r2, #MACH_TYPE_W90N745
+	str     r2, [r9]
+
+        mov fp, #0
+        b	start_kernel
+        
+LC0:	.long	__bss_start
+        .long	processor_id
+        .long	_end
+	.long   __machine_arch_type
+        .long	init_task_union+8192
+	
+W90N745_PROCESSOR_TYPE:
+	.long	0x32103201
+#endif
+
+
 #if defined(CONFIG_BOARD_SNDS100)
 
         adr	r5, LC0
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/kernel/irq.c b/uClinux-2.4.20-uc1/arch/armnommu/kernel/irq.c
index 227cd8f..f686290 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/kernel/irq.c
+++ b/uClinux-2.4.20-uc1/arch/armnommu/kernel/irq.c
@@ -35,6 +35,8 @@
 
 #include <asm/arch/irq.h>	/* pick up fixup_irq definition */
 
+#include <linux/w83977.h>
+
 /*
  * Maximum IRQ count.  Currently, this is arbitary.  However, it should
  * not be set too low to prevent false triggering.  Conversely, if it
@@ -156,6 +158,10 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 	struct irqaction * action;
 	int cpu;
 
+#ifdef CONFIG_BOARD_W90N745
+	irq = irq >> 2;
+#endif
+
 #ifdef CONFIG_BOARD_SNDS100
         /*
          * FIXME: This is not the best place to put this work around. 
@@ -163,7 +169,9 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 	CLEAR_PEND_INT(irq);
 #endif
 
+#ifndef CONFIG_BOARD_W90N745
 	irq = fixup_irq(irq);
+#endif
 
 	/*
 	 * Some hardware gives randomly wrong interrupts.  Rather
@@ -172,12 +180,21 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 	if (irq >= NR_IRQS)
 		goto bad_irq;
 
+#ifdef CONFIG_BOARD_W90N745
+	if (irq <= 0)
+		goto bad_irq;
+#endif
+
 	desc = irq_desc + irq;
 
 	spin_lock(&irq_controller_lock);
 	desc->mask_ack(irq);
 	spin_unlock(&irq_controller_lock);
 
+#ifdef CONFIG_BOARD_W90N745
+	irq = fixup_irq(irq);
+#endif
+
 	cpu = smp_processor_id();
 	irq_enter(cpu, irq);
 	kstat.irqs[cpu][irq]++;
@@ -223,6 +240,10 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 
 	irq_exit(cpu, irq);
 
+#ifdef CONFIG_BOARD_W90N745
+	DWORD_WRITE(AIC_EOSCR, 1);
+#endif
+
 	if (softirq_pending(cpu))
 		do_softirq();
 	return;
@@ -513,6 +534,10 @@ void __init init_irq_proc(void)
 {
 }
 
+#ifdef CONFIG_BOARD_W90N745
+extern void init_EBI(void);
+#endif
+
 void __init init_IRQ(void)
 {
 	extern void init_dma(void);
@@ -527,6 +552,19 @@ void __init init_IRQ(void)
 		irq_desc[irq].unmask   = dummy_mask_unmask_irq;
 	}
 
+#ifdef CONFIG_BOARD_W90N745
+	CSR_WRITE(AIC_MDCR, 0x7FFFE); /* disable all interrupts */
+	
+	CSR_WRITE(CAHCNF, 0x0);/*Close Cache*/
+	CSR_WRITE(CAHCON, 0x87);/*Flush Cache*/
+	while(CSR_READ(CAHCON)!=0) {}
+	CSR_WRITE(CAHCNF, 0x7);/*Open Cache*/
+#endif
+
 	init_arch_irq();
 	init_dma();
+	
+#ifdef CONFIG_W83977	
+	init_EBI();
+#endif
 }
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/kernel/setup.c b/uClinux-2.4.20-uc1/arch/armnommu/kernel/setup.c
index a269e85..05af4f1 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/kernel/setup.c
+++ b/uClinux-2.4.20-uc1/arch/armnommu/kernel/setup.c
@@ -35,6 +35,12 @@
 //#define MEM_SIZE	(8*1024*1024)
 #define MEM_SIZE (END_MEM-PAGE_OFFSET)	// FIXME
 
+#ifndef DRAM_SIZE
+#define MEM_SIZE	(7*1024*1024)
+#else
+#define MEM_SIZE        DRAM_SIZE
+#endif
+
 #endif
 
 #ifndef CONFIG_CMDLINE
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/Makefile b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/Makefile
new file mode 100644
index 0000000..498b599
--- /dev/null
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET		:= W90N745.o
+
+# Object file lists.
+
+obj-y			:= $(patsubst %.c, %.o, $(wildcard *.c))
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+export-objs		:= 
+
+include $(TOPDIR)/Rules.make
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/arch.c b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/arch.c
new file mode 100644
index 0000000..815beb8
--- /dev/null
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/arch.c
@@ -0,0 +1,24 @@
+/*
+ *  linux/arch/arm/mach-W90N745/arch.c
+ *
+ *  Architecture specific fixups.  This is where any
+ *  parameters in the params struct are fixed up, or
+ *  any additional architecture specific information
+ *  is pulled from the params struct.
+ */
+#include <linux/tty.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/init.h>
+
+#include <asm/elf.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+extern void genarch_init_irq(void);
+
+MACHINE_START(W90N745, "W90N745")
+       MAINTAINER("Shirley yu")
+       INITIRQ(genarch_init_irq)
+MACHINE_END
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/irq.c b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/irq.c
new file mode 100644
index 0000000..f8c34be
--- /dev/null
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/irq.c
@@ -0,0 +1,39 @@
+/*
+*  linux/arch/armnommu/mach-W90N745/irq.c
+*  2003 clyu <clyu2@winbond.com.tw>
+*/
+#include <linux/init.h>
+
+#include <asm/mach/irq.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+
+void W90N745_mask_irq(unsigned int irq)
+{
+	INT_DISABLE(irq);
+}
+
+void W90N745_unmask_irq(unsigned int irq)
+{
+	INT_ENABLE(irq);
+}
+
+void W90N745_mask_ack_irq(unsigned int irq)
+{
+	INT_DISABLE(irq);
+}
+
+void W90N745_int_init()
+{
+	//int i=0;
+	//IntPend = 0x1FFFFF;
+	CSR_WRITE(AIC_MDCR,0xFFFFFFFF);
+	CSR_WRITE(AIC_SCR9,0x41);
+	CSR_WRITE(AIC_SCR13,0x41);
+	//for(i=6;i<=18;i++)
+	//	IntScr(i,0x41);
+	//IntMode = INT_MODE_IRQ;
+	//INT_ENABLE(INT_GLOBAL);
+}
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/time.c b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/time.c
new file mode 100644
index 0000000..067085f
--- /dev/null
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mach-W90N745/time.c
@@ -0,0 +1,30 @@
+/*
+ * time.c  Timer functions for Winbond W90N745
+ */
+
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <linux/interrupt.h>
+
+struct irqaction watchdog_irq = {
+	name: "watchdog",
+};
+
+unsigned long winbond_gettimeoffset (void)
+{
+	return 0;
+}
+
+void winbond_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        do_timer(regs);
+}
+
+void winbond_watchdog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	CSR_WRITE(WTCR, (CSR_READ(WTCR)&0xF7)|0x01);
+}
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mm/init.c b/uClinux-2.4.20-uc1/arch/armnommu/mm/init.c
index 87cf937..4d98862 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/mm/init.c
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mm/init.c
@@ -368,7 +368,7 @@ static __init void reserve_node_zero(unsigned int bootmap_pfn, unsigned int boot
 	 */
 
 	if (machine_is_integrator() || machine_is_snds100() ||
-            machine_is_evS3C4530HEI() )
+            machine_is_evS3C4530HEI() || machine_is_W90N745() )
 		reserve_bootmem_node(pgdat, 0, __pa(&_stext));
 
 	/*
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/mm/proc-arm6,7.S b/uClinux-2.4.20-uc1/arch/armnommu/mm/proc-arm6,7.S
index 65b2eef..f411400 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/mm/proc-arm6,7.S
+++ b/uClinux-2.4.20-uc1/arch/armnommu/mm/proc-arm6,7.S
@@ -429,6 +429,10 @@ cpu_s3c4510b_name:
 		.asciz	"S3C4510B"
 cpu_s3c4530_name:
 		.asciz  "S3C4530A01"
+cpu_W90N745_manu_name:
+		.asciz	"Winbond"
+cpu_W90N745_name:
+		.asciz	"W90N745"
 		.align
 
 		.section ".text.init", #alloc, #execinstr
@@ -631,6 +635,12 @@ cpu_s3c4530_info:
                 .long   cpu_s3c4530_name
                 .size   cpu_s3c4530_info, . - cpu_s3c4530_info
 
+		.type   cpu_W90N745_info, #object
+cpu_W90N745_info:
+		.long   cpu_W90N745_manu_name
+		.long   cpu_W90N745_name
+		.size   cpu_W90N745_info, . - cpu_W90N745_info
+
 		.type	cpu_arm710_info, #object
 cpu_arm710_info:
 		.long	cpu_armvlsi_name
@@ -778,3 +788,15 @@ __s3c3410_proc_info:
 		.long	arm7_processor_functions	@ info
 		.size	__s3c3410_proc_info, . - __s3c3410_proc_info
 
+		.type   __W90N745_proc_info, #object
+__W90N745_proc_info:
+		.long	0x32100000			@ cpu_val
+		.long	0xffff0000			@ cpu_mask
+		.long	0x00000c1e			@ __cpu_mmu_flags
+		b	__arm7_setup			@ __cpu_flush
+		.long	cpu_arch_name			@ arch_name
+		.long	cpu_elf_name			@ elf_name
+		.long	HWCAP_SWP | HWCAP_26BIT		@ elf_hwcap
+		.long	cpu_W90N745_info		@ info
+		.long	arm7_processor_functions	@ info
+		.size	__W90N745_proc_info, . - __W90N745_proc_info
diff --git a/uClinux-2.4.20-uc1/arch/armnommu/tools/mach-types b/uClinux-2.4.20-uc1/arch/armnommu/tools/mach-types
index 7fd21ad..b9feae3 100644
--- a/uClinux-2.4.20-uc1/arch/armnommu/tools/mach-types
+++ b/uClinux-2.4.20-uc1/arch/armnommu/tools/mach-types
@@ -104,6 +104,7 @@ dsc21                   ARCH_DSC21              DSC21                   115
 snds100			BOARD_SNDS100		SNDS100			90
 evS3C4530HEI		BOARD_EVS3C4530HEI	EVS3C4530HEI		164
 S3C3410X		BOARD_SMDK40100		S3C3410			165
+W90N745			ARCH_WINBOND		W90N745			181
 ta7s			ARCH_TA7S		TA7S			334
 
 
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/bib.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/bib.h
new file mode 100644
index 0000000..24c4932
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/bib.h
@@ -0,0 +1,27 @@
+#ifndef _BIB_H
+#define _BIB_H
+#include <asm/arch/cdefs.h>
+//---------------------------------------------------------------------------
+typedef struct _t_bootloaer_info
+{
+	UINT32 length;
+	UINT32 type;
+	char mac0[6];
+	char ip0[6];
+	char mac1[6];
+	char ip1[6];
+	UINT32 cache;
+	UINT32 dhcp;
+	UINT32 net_mac;
+	UINT32 phy;
+	UINT32 buf_base;
+	UINT32 buf_size;
+} tbl_info;
+
+#define BOOTLOADER_INFO	0x1
+
+extern int _dhcp;
+
+
+//---------------------------------------------------------------------------
+#endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/cdefs.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/cdefs.h
new file mode 100644
index 0000000..c28c011
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/cdefs.h
@@ -0,0 +1,24 @@
+#ifndef CDEFS_H
+#define CDEFS_H
+
+#define AHBBASE	0xFFF00000
+#define FLASH_BASE	(0x7F000000)
+#define ROMCON	(AHBBASE + 0x1004)
+#define W90N745_FLASH_SIZE	(0x40000<<(( *((UINT *)ROMCON)>>16 )&0x7))
+#define FLASH_BLOCK_SIZE	(0x10000)
+#define FLASH_SIZE	(W90N745_FLASH_SIZE)
+//------------------------------------------------------------------------------
+#define UINT16	u16
+typedef int INT;
+typedef int SIGNED;
+typedef unsigned int UNSIGNED;
+typedef unsigned int UINT;
+typedef unsigned int UINT32;
+typedef unsigned char UCHAR;
+typedef char CHAR;
+typedef void VOID;
+typedef unsigned long ULONG;
+#define NULL	0
+
+//------------------------------------------------------------------------------
+#endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/dma.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/dma.h
new file mode 100644
index 0000000..0f4c27b
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/dma.h
@@ -0,0 +1,15 @@
+/*
+ * asm/arch-armnommu/arch-W90N745/dma.h:
+ * Mindspeed 2001
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS 0x000700000
+//#define MAX_DMA_CHANNELS        13
+#define MAX_DMA_CHANNELS        0
+
+#define arch_dma_init(dma_chan)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/firmware.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/firmware.h
new file mode 100644
index 0000000..fcfb815
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/firmware.h
@@ -0,0 +1,13 @@
+typedef struct FirmWare{
+	int flag;
+	int length_bin;
+	int length_img;
+}FirmWare;
+
+#define BINZIP	0x00000001
+#define IMGZIP	0x00000002
+
+#define ISBINZIP(flag)	 ((flag)&0x00000001)
+#define ISBINUNZIP(flag) !((flag)&0x00000001)
+#define ISIMGZIP(flag)	 ((flag)&0x00000002)
+#define ISIMGUNZIP(flag) !((flag)&0x00000002)
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/hardware.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/hardware.h
new file mode 100644
index 0000000..9921514
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/hardware.h
@@ -0,0 +1,444 @@
+/********************************************************/
+/*							*/
+/* Winbond W90N745					*/
+/* PC34 Lsshi				*/
+/*							*/
+/********************************************************/
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * define W90N745 CPU master clock
+ */
+#define MHz		1000000
+#define fMCLK_MHz	(15 * MHz)
+#define fMCLK		(fMCLK_MHz / MHz)
+#define MCLK2		(fMCLK_MHz / 2)
+
+#define pcibios_assign_all_busses()        1
+
+/*
+ * ASIC Address Definition
+ */
+
+#define Base_Addr		0xFFF00000
+#define AHB_IO_BASE		Base_Addr
+#define APB_IO_BASE		0xFFF80000
+
+#define VPint	*(volatile unsigned int *)
+#define VPshort	*(volatile unsigned short *)
+#define VPchar	*(volatile unsigned char *)
+
+#ifndef CSR_WRITE
+#   define CSR_WRITE(addr,data)	(VPint(addr) = (data))
+#endif
+
+#ifndef CSR_READ
+#   define CSR_READ(addr)	(VPint(addr))
+#endif
+
+#ifndef CAM_Reg
+#   define CAM_Reg(x)		(VPint(CAMBASE+(x*0x4)))
+#endif
+
+/* ************************ */
+/* System Manager Registers */
+/* ************************ */
+#define PDID		(Base_Addr+0x00000)
+#define ARBCON		(Base_Addr+0x00004)
+#define PLLCON		(Base_Addr+0x00008)
+#define CLKSEL		(Base_Addr+0x0000c)
+
+/*****************************/
+/* Cache Control Register Map*/
+/*****************************/
+#define CAHCNF		(Base_Addr+0x02000)
+#define CAHCON		(Base_Addr+0x02004)
+#define CAHADR		(Base_Addr+0x02008)
+
+#define NON_CANCHABLE 0x80000000
+//#define NONCACHE
+/*****************************/
+/* EBI Control Registers Map */
+/*****************************/
+#define EBICON		(Base_Addr+0x01000)
+#define ROMCON0		(Base_Addr+0x01004)
+#define DRAMCON0	(Base_Addr+0x01008)
+#define DRAMCON1	(Base_Addr+0x0100c)
+#define SDTIME0		(Base_Addr+0x01010)
+#define SDTIME1		(Base_Addr+0x01014)
+
+/********************************/
+/* GPIO Controller Registers Map*/
+/********************************/
+#define GPIO_CFG		(Base_Addr+0x83000) /*	GPIO Configuration Register */
+#define GPIO_DIR		(Base_Addr+0x83004) /*	GPIO Direction Register */
+#define GPIO_DATAOUT	(Base_Addr+0x83008) /*	GPIO Data Output Register */
+#define GPIO_DATAIN		(Base_Addr+0x8300c) /*	GPIO Data Input Register */
+#define GPIO_DEBNCE		(Base_Addr+0x83010) /*	GPIO De-bounce Control Register */
+#define GPIO_INV		(Base_Addr+0x83014) /*	GPIO Data Input Inverse Register */
+
+
+/* *********************** */
+/* Ethernet BDMA Registers */
+/* *********************** */
+#define BDMATXCON	(Base_Addr+0x9000)
+#define BDMARXCON	(Base_Addr+0x9004)
+#define BDMATXPTR	(Base_Addr+0x9008)
+#define BDMARXPTR	(Base_Addr+0x900C)
+#define BDMARXLSZ	(Base_Addr+0x9010)
+#define BDMASTAT	(Base_Addr+0x9014)
+#define CAMBASE		(Base_Addr+0x9100)
+/*
+ * CAM		0x9100 ~ 0x917C
+ * BDMATXBUF	0x9200 ~ 0x92FC
+ * BDMARXBUF	0x9800 ~ 0x99FC
+ */
+
+/* ********************** */
+/* Ethernet MAC Registers */
+/* ********************** */
+
+#define  MAC_BASE  	(Base_Addr+0x3000)
+
+#if 0
+#define MACON		(Base_Addr+0xA000)
+#define CAMCON		(Base_Addr+0xA004)
+#define MACTXCON	(Base_Addr+0xA008)
+#define MACTXSTAT	(Base_Addr+0xA00C)
+#define MACRXCON	(Base_Addr+0xA010)
+#define MACRXSTAT	(Base_Addr+0xA014)
+#define STADATA		(Base_Addr+0xA018)
+#define STACON		(Base_Addr+0xA01C)
+#define CAMEN		(Base_Addr+0xA028)
+#define EMISSCNT	(Base_Addr+0xA03C)
+#define EPZCNT		(Base_Addr+0xA040)
+#define ERMPZCNT	(Base_Addr+0xA044)
+#define EXTSTAT		(Base_Addr+0x9040)
+#endif
+/* ************************ */
+/* HDLC Channel A Registers */
+/* ************************ */
+
+/* ************************ */
+/* HDLC Channel B Registers */
+/* ************************ */
+
+/* ******************* */
+/* I/O Ports Registers */
+/* ******************* */
+#define IOPMOD		(Base_Addr+0x5000)
+#define IOPCON		(Base_Addr+0x5004)
+#define IOPDATA		(Base_Addr+0x5008)
+
+
+/* ****************************** */
+/* AIC Registers Map			  */
+/* ****************************** */
+#define AIC_SCR1	(Base_Addr+0x82004)
+#define AIC_SCR2	(Base_Addr+0x82008)
+#define AIC_SCR3	(Base_Addr+0x8200c)
+#define AIC_SCR4	(Base_Addr+0x82010)
+#define AIC_SCR5	(Base_Addr+0x82014)
+#define AIC_SCR6	(Base_Addr+0x82018)
+#define AIC_SCR7	(Base_Addr+0x8201c)
+#define AIC_SCR8	(Base_Addr+0x82010)
+#define AIC_SCR9	(Base_Addr+0x82024)
+#define AIC_SCR10	(Base_Addr+0x82028)
+#define AIC_SCR11	(Base_Addr+0x8202c)
+#define AIC_SCR12	(Base_Addr+0x82030)
+#define AIC_SCR13	(Base_Addr+0x82034)
+#define AIC_SCR14	(Base_Addr+0x82038)
+#define AIC_SCR15	(Base_Addr+0x8203c)
+#define AIC_SCR16	(Base_Addr+0x82040)
+
+#define AIC_SCR17	(Base_Addr+0x82044)
+#define AIC_SCR18	(Base_Addr+0x82048)
+
+#define AIC_SCR19	(Base_Addr+0x8204c)
+#define AIC_SCR20	(Base_Addr+0x82050)
+#define AIC_SCR21	(Base_Addr+0x82054)
+#define AIC_SCR22	(Base_Addr+0x82058)
+#define AIC_SCR23	(Base_Addr+0x8205c)
+#define AIC_SCR24	(Base_Addr+0x82060)
+#define AIC_SCR25	(Base_Addr+0x82064)
+#define AIC_SCR26	(Base_Addr+0x82068)
+#define AIC_SCR27	(Base_Addr+0x8206c)
+#define AIC_SCR28	(Base_Addr+0x82070)
+#define AIC_SCR29	(Base_Addr+0x82074)
+#define AIC_SCR30	(Base_Addr+0x82078)
+
+#define AIC_IRSR	(Base_Addr+0x82100)
+#define AIC_IASR	(Base_Addr+0x82104)
+#define AIC_ISR		(Base_Addr+0x82108)
+#define AIC_IPER	(Base_Addr+0x8210c)
+#define AIC_ISNR	(Base_Addr+0x82110)
+#define AIC_IMR		(Base_Addr+0x82114)
+#define AIC_OISR	(Base_Addr+0x82118)
+#define AIC_MECR	(Base_Addr+0x82120)
+#define AIC_MDCR	(Base_Addr+0x82124)
+#define AIC_SSCR	(Base_Addr+0x82128)
+#define AIC_SCCR	(Base_Addr+0x8212c)
+#define AIC_EOSCR	(Base_Addr+0x82130)
+#define AIC_TEST	(Base_Addr+0x82200)
+
+
+#define IntScr(index,value)		(VPint(Base_Addr+0x82000+4*index)=value)
+#define IntPend		(VPint(AIC_EOSCR))
+#define IntMask		(VPint(AIC_MDCR))
+#define IntUnMask	(VPint(AIC_MECR))
+
+#define INT_ENABLE(n)		IntUnMask = (1<<(n))
+#define INT_DISABLE(n)		IntMask = (1<<(n))
+//#define CLEAR_PEND_INT(n)	IntPend = (0)
+//#define SET_PEND_INT(n)		IntPndTst |= (1<<(n))
+
+/* ***************** */
+/* I2C Bus Registers */
+/* ***************** */
+
+/* ************** */
+/* GDMA Registers */
+/* ************** */
+
+/* ************** */
+/* UART Registers */
+/* ************** */
+
+#define DEBUG_CONSOLE	(0)
+
+#define COM_TX			(Base_Addr+0x80000)
+#define COM_RX			(Base_Addr+0x80000)
+#define COM_DLL 		(Base_Addr+0x80000)
+#define COM_DLM 		(Base_Addr+0x80004)
+#define COM_IER 		(Base_Addr+0x80004)
+#define COM_IIR 		(Base_Addr+0x80008)
+#define COM_FCR 		(Base_Addr+0x80008)
+#define COM_LCR 		(Base_Addr+0x8000c)
+#define COM_MCR 		(Base_Addr+0x80010)
+#define COM_LSR 		(Base_Addr+0x80014)
+#define COM_MSR 		(Base_Addr+0x80018)
+#define COM_TOR 		(Base_Addr+0x8001c)
+
+#define UART_BASE0		COM_TX
+
+#define UART_BASE1		(Base_Addr+0x80100)
+#define UART_BASE2		(Base_Addr+0x80200)
+#define UART_BASE3		(Base_Addr+0x80300)
+
+#if DEBUG_CONSOLE == 0
+	#define DEBUG_TX_BUFF_BASE	COM_TX
+	#define DEBUG_RX_BUFF_BASE	COM_RX
+	#define DEBUG_UARTLCON_BASE	COM_LCR
+	#define DEBUG_UARTCONT_BASE	COM_LCR                  
+	#define DEBUG_UARTBRD_BASE	COM_DLL
+	#define DEBUG_CHK_STAT_BASE	COM_IIR
+#endif
+
+#define DEBUG_ULCR_REG_VAL	(0x3)
+#define DEBUG_ULCR_REG_VAL	(0x3)
+#define DEBUG_UDLL_REG_VAL	(0x6)
+#define DEBUG_RX_CHECK_BIT	(0X20)
+#define DEBUG_TX_CAN_CHECK_BIT	(0X40)
+#define DEBUG_TX_DONE_CHECK_BIT	(0X80)
+
+
+/* **************** */
+/* Timers Registers */
+/* **************** */
+#define TCR0		(Base_Addr+0x81000)
+#define TCR1		(Base_Addr+0x81004)
+#define TICR0		(Base_Addr+0x81008)
+#define TICR1		(Base_Addr+0x8100c)
+#define TDR0		(Base_Addr+0x81010)
+#define TDR1		(Base_Addr+0x81014)
+#define TISR		(Base_Addr+0x81018)
+#define WTCR		(Base_Addr+0x8101c)
+
+/*******************/
+/* SYSCFG Register */
+/*******************/
+
+#define SYS_INIT_BASE	EXTDBWTH
+#define rSYSCFG		(0x87FFFF90)	/* disable Cache/Write buffer */
+
+/**********************************/
+/* System Memory Control Register */
+/**********************************/
+#define DSR0		(2<<0)	/* ROM Bank0 */
+#define DSR1		(0<<2)	/* 0: Disable, 1: Byte, 2: Half-Word, 3: Word */
+#define DSR2		(0<<4)
+#define DSR3		(0<<6)
+#define DSR4		(0<<8)
+#define DSR5		(0<<10)
+#define DSD0		(2<<12) /* RAM Bank0 */
+#define DSD1		(0<<14)
+#define DSD2		(0<<16)
+#define DSD3		(0<<18)
+#define DSX0		(0<<20)	/* EXTIO0 */
+#define DSX1		(0<<22)
+#define DSX2		(0<<24)
+#define DSX3		(0<<26)
+
+#define rEXTDBWTH	(DSR0|DSR1|DSR2|DSR3|DSR4|DSR5 | DSD0|DSD1|DSD2|DSD3 | DSX0|DSX1|DSX2|DSX3)
+
+/****************************************/
+/* ROMCON0: ROM Bank 0 Control Register */
+/****************************************/
+#define PMC0		(0x0<<0)	/*00: Normal ROM   01: 4 word page*/
+					/*10: 8 word page  11:16 word page*/
+#define tPA0		(0x0<<2)	/*00: 5 cycles     01: 2 cycles*/
+					/*10: 3 cycles     11: 4 cycles*/
+#define tACC0		(0x6<<4)	/*000: Disable bank 001: 2 cycles*/
+					/*010: 3 cycles     011: 4 cycles*/
+					/*110: 7 cycles     111: Reserved*/
+#define ROM_BASE0_R	((0x00000000>>16)<<10)
+#define ROM_NEXT0_R	((0x00200000>>16)<<20)
+#define ROM_BASE0_B	((0x01000000>>16)<<10)
+#define ROM_NEXT0_B	((0x01200000>>16)<<20)
+#define rROMCON0_R	(ROM_NEXT0_R|ROM_BASE0_R|tACC0|tPA0|PMC0)
+#define rROMCON0_B	(ROM_NEXT0_B|ROM_BASE0_B|tACC0|tPA0|PMC0)
+
+#define rROMCON1	0x0
+#define rROMCON2	0x0
+#define rROMCON3	0x0
+#define rROMCON4	0x0
+#define rROMCON5	0x0
+
+
+/********************************************/
+/* SDRAMCON0: SDRAM Bank 0 Control Register */
+/********************************************/
+#define StRC0		(0x1<<7)
+#define StRP0		(0x3<<8)
+#define SDRAM_BASE0_R	((0x01000000>>16)<<10)
+#define SDRAM_NEXT0_R	((0x01800000>>16)<<20)
+#define SDRAM_BASE0_B	((0x00000000>>16)<<10)
+#define SDRAM_NEXT0_B	((0x00800000>>16)<<20)
+#define SCAN0		(0x0<<30)
+#define rSDRAMCON0_R	(SCAN0|SDRAM_NEXT0_R|SDRAM_BASE0_R|StRP0|StRC0)
+#define rSDRAMCON0_B	(SCAN0|SDRAM_NEXT0_B|SDRAM_BASE0_B|StRP0|StRC0)
+
+#define rSDRAMCON1	0x0
+#define rSDRAMCON2	0x0
+#define rSDRAMCON3	0x0
+
+/************************************************/
+/* DRAM Refresh & External I/O Control Register */
+/************************************************/
+#define ExtIOBase	(0x360<<0)
+#define VSF		(0x1<<15)
+#define REN		(0x1<<16)
+#define tCHR		(0x0<<17)
+#define tCSR		(0x0<<20)
+#define RefCountValue	((2048+1-(16*fMCLK))<<21)
+#define rREFEXTCON	(RefCountValue|tCSR|tCHR|REN|VSF|ExtIOBase)
+
+/********/
+/* Misc */
+/********/
+
+#define TMOD_TIMER0_VAL	0x3	/* Timer0  TOGGLE, and Run */
+#define TAG_BASE	0x11000000
+
+#define HARD_RESET_NOW()
+
+/*PCI*/
+#define PCIBIOS_MIN_IO		0x6000
+#define PCIBIOS_MIN_MEM 	0x01000000
+
+//*************************************************************************
+
+//lsshi add 2004-1-2 12:28
+#ifndef DWORD_WRITE // 32-bit
+#   define DWORD_WRITE(addr,data)	(*((unsigned int volatile *)(addr))=data)
+#endif
+
+#ifndef DWORD_READ
+#   define DWORD_READ(addr)	(*((unsigned int volatile *)(addr)))
+#endif
+
+#ifndef WORD_WRITE //16-bit
+#   define WORD_WRITE(addr,data)	(*((unsigned short volatile *)(addr))=data)
+#endif
+
+#ifndef WORD_READ
+#   define WORD_READ(addr)		(*((unsigned short volatile *)(addr)))
+#endif
+
+#ifndef BYTE_WRITE //8-bit
+#   define BYTE_WRITE(addr,data)	(*((unsigned char volatile *)(addr))=data)
+#endif
+
+#ifndef BYTE_READ
+#   define BYTE_READ(addr)		(*((unsigned char volatile *)(addr)))
+#endif
+
+
+
+/* EBI 0-3 control Registers Map */
+/*****************************/
+#define EXT0CON	(Base_Addr+0x01018)
+#define EXT1CON	(Base_Addr+0x0101c)
+#define EXT2CON	(Base_Addr+0x01020)
+#define EXT3CON	(Base_Addr+0x01024)
+
+//EBI Config bits
+#define SIZE_256k		(0<<16)
+#define SIZE_512k		(1<<16)
+#define SIZE_1M		(2<<16)
+#define SIZE_16M		(6<<16)
+#define SIZE_32M		(7<<16)
+
+#define ADRS			(1<<15)
+#define tACC			(15<<11)
+#define tCOH			(7<<8)
+#define tACS			(7<<5)
+#define tCOS			(7<<2)
+
+#define DBWD0		(2)//16-bit bus width for DoC
+#define DBWD1		(1)//8-bit bus width
+#define DBWD2		(1)
+#define DBWD3		(1)
+
+#define EXT0_BASS	0x70000000
+#define EXT1_BASS	0x73000000
+#define EXT2_BASS	0x74000000
+#define EXT3_BASS	0x78000000
+
+
+#define EXT0CON_DATA	((EXT0_BASS<<1)|SIZE_32M|ADRS|tACC|tCOH|tACS|tCOS|DBWD0)
+#define EXT1CON_DATA	((EXT1_BASS<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|DBWD1)
+#define EXT2CON_DATA	((EXT2_BASS<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|DBWD2)
+#define EXT3CON_DATA	((EXT3_BASS<<1)|SIZE_32M|ADRS|tACC|tCOH|tACS|tCOS|DBWD3)
+
+
+//EBI Device Base address
+//define for DOC
+#define DOC_BASE_ADDR		EXT0_BASS
+//define for LCM
+#define LCM_BASE_ADDR		(EXT3_BASS|0x1000000)
+#define PLD_BASE_ADDR		(EXT3_BASS|0x80000000)
+//define for W83977
+#define W83977AF_BASE_ADDR	EXT1_BASS
+#define W83977EF_BASE_ADDR	EXT2_BASS
+
+//USB Host/Device Base addr
+#define USB_HOST		(AHB_IO_BASE+0x5000) // USB Host
+#define	USB_DEVICE    	(AHB_IO_BASE+0x6000) /* USB Device */
+
+
+#ifndef CSR_READ_OFFSET
+	#define CSR_READ_OFFSET(addr,offset)	*((volatile unsigned char *)((addr)+offset))
+#endif
+
+
+ // Routines to Enable/Disable Interrupts
+#define Enable_Int(n)     (VPint(AIC_MECR)) = (1<<(n))
+#define Disable_Int(n)    (VPint(AIC_MDCR)) = (1<<(n))
+#define Enable_Int_All()  (VPint(AIC_MECR)) = 0xffff
+#define Disable_Int_All() (VPint(AIC_MDCR)) = 0xffff
+
+//***************************************************************************
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/io.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/io.h
new file mode 100644
index 0000000..4ccd6e4
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/io.h
@@ -0,0 +1,39 @@
+/*
+ * linux/include/asm-armnommu/arch-W90N745/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997	RMK	Created.
+ *  07-04-1999	RMK	Major cleanup
+ *  02-19-2001  gjm     Leveraged for armnommu/dsc21
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/*
+ * kernel/resource.c uses this to initialize the global ioport_resource struct
+ * which is used in all calls to request_resource(), allocate_resource(), etc.
+ * --gmcnutt
+ */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * If we define __io then asm/io.h will take care of most of the inb & friends
+ * macros. It still leaves us some 16bit macros to deal with ourselves, though.
+ * We don't have PCI or ISA on the dsc21 so I dropped __mem_pci & __mem_isa.
+ * --gmcnutt
+ */
+#define PCIO_BASE 0
+#define __io(a) (PCIO_BASE + (a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
+
+/*
+ * Defining these two gives us ioremap for free. See asm/io.h.
+ * --gmcnutt
+ */
+#define iomem_valid_addr(iomem,sz) (1)
+#define iomem_to_phys(iomem) (iomem)
+
+#endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irq.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irq.h
new file mode 100644
index 0000000..8f18c64
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irq.h
@@ -0,0 +1,38 @@
+/*
+ * asm/arch-W90N745/irq.h:
+ * PC34 Lsshi
+ */
+
+#ifndef __ASM_ARCH_IRQ_H__
+#define __ASM_ARCH_IRQ_H__
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/irqs.h>
+
+#define fixup_irq(x) (x)
+
+extern void W90N745_mask_irq(unsigned int irq);
+extern void W90N745_unmask_irq(unsigned int irq);
+extern void W90N745_mask_ack_irq(unsigned int irq);
+extern void W90N745_int_init(void);
+
+static __inline__ void irq_init_irq(void)
+{
+	unsigned long flags;
+	int irq;
+
+	save_flags_cli(flags);
+	W90N745_int_init();
+	restore_flags(flags);
+
+	for (irq = 0; irq < NR_IRQS; irq++) {
+		irq_desc[irq].valid	= 1;
+		irq_desc[irq].probe_ok	= 1;
+		irq_desc[irq].mask_ack	= W90N745_mask_ack_irq;
+		irq_desc[irq].mask	= W90N745_mask_irq;
+		irq_desc[irq].unmask	= W90N745_unmask_irq;
+	}
+}
+#endif /* __ASM_ARCH_IRQ_H__ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irqs.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irqs.h
new file mode 100644
index 0000000..435fd94
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/irqs.h
@@ -0,0 +1,63 @@
+/*
+ * asm/arch-W90N745/irqs.h:
+ * PC34 Lsshi
+ */
+#ifndef __ASM_ARCH_IRQS_H__
+#define __ASM_ARCH_IRQS_H__
+#define NR_IRQS		32
+//#define VALID_IRQ(i)	(i<=10 ||(i>=13 && i<NR_IRQS))
+#define VALID_IRQ(i)	(i<NR_IRQS)
+
+#define INT_WDTINT		1 	/* Watch Dog Timer Interrupt */
+
+#define INT_nIRQ0		2 	/* External Interrupt 0 */
+#define INT_nIRQ1		3 	/* External Interrupt 1 */
+#define INT_nIRQ2		4 	/* External Interrupt 2 */
+#define INT_nIRQ3		5 	/* External Interrupt 3 */
+
+#define INT_AC97		6 	/* AC97 Interrupt */
+#define INT_LCD			7 	/* LCD Controller Interrupt */
+#define INT_RTC			8 	/* RTC Controller Interrupt */
+
+#define INT_UARTINT		9 	/* UART 0 Interrupt */
+#define INT_UART1		10 	/* UART 1 Interrupt */
+#define INT_UART2		11	/* UART 2 Interrupt */
+#define INT_UART3		12 	/* UART 3 Interrupt */
+
+#define INT_TINT0		13 	/* Timer Interrupt 0 */
+#define INT_TINT1		14	/* Timer Interrupt 1 */
+
+
+#define INT_USBINT0		15 /* USB Host Interrupt 0 */
+#define INT_USBINT1		16 /* USB Host Interrupt 1 */
+
+
+#define INT_EMCTXINT0	17 /* EMC TX Interrupt 0 */
+#define INT_EMCRXINT0	18 /* EMC RX Interrupt 0 */
+#define INT_EMCTXINT1	17 /* EMC TX Interrupt 1 */ /* for debugging */
+#define INT_EMCRXINT1	18 /* EMC RX Interrupt 1 */ /* for debugging */
+
+#define INT_GDMAINT0	19 /* GDMA Channel Interrupt 0 */
+#define INT_GDMAINT1	20 /* GDMA Channel Interrupt 1 */
+
+#define INT_SDIO		21 	/* SDIO Interrupt */
+#define INT_USBD		22 	/* USB Device Interrupt */
+#define INT_SC0			23 	/* SmartCard Interrupt 0 */
+#define INT_SC1			24 	/* SmartCard Interrupt 1 */
+#define INT_I2C0		25 	/* I2C Interrupt 0 */
+#define INT_I2C1		26 	/* I2C Interrupt 1 */
+#define INT_SPI			27 	/* SPI Interrupt */
+#define INT_PWM			28 	/* PWM Timer Interrupt */
+#define INT_KEYPAD		29 	/* Keypad Interrupt */
+#define INT_PS2			30 	/* PS2 Interrupt */
+
+#define INT_Reserved0	31
+//#define INT_Reserved1	12
+
+//#define INT_IIC		20
+//#define INT_GLOBAL	31
+
+#define IRQ_TIMER	INT_TINT0
+
+
+#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/memory.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/memory.h
new file mode 100644
index 0000000..785dd81
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/memory.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-armnommu/arch-W90N745/memory.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ * 2001 Mindspeed
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define TASK_SIZE	(0x01a00000UL)
+#define TASK_SIZE_26	TASK_SIZE
+
+#if 0
+extern unsigned long _end_kernel;
+#define PHYS_OFFSET    ((unsigned long) &_end_kernel)
+#else
+#define PHYS_OFFSET    (DRAM_BASE)
+#endif
+#define PAGE_OFFSET PHYS_OFFSET
+#define END_MEM     (DRAM_BASE + DRAM_SIZE)
+#endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/param.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/param.h
new file mode 100644
index 0000000..8a1d92b
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/param.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_ASM_PARAM_H__
+#define __ARCH_ASM_PARAM_H__
+
+/* nothing for now */
+
+#endif /* __ARCH_ASM_PARAM_H__ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/processor.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/processor.h
new file mode 100644
index 0000000..c5145df
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/processor.h
@@ -0,0 +1,15 @@
+/*
+ * uclinux/include/asm-armnommu/arch-W90N745/mmu.h
+ *
+ */
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+#define EISA_bus 0
+#define EISA_bus__is_a_macro
+#define MCA_bus 0
+#define MCA_bus__is_a_macro
+
+#define TASK_SIZE (0x01a00000UL)
+
+#endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/serial.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/serial.h
new file mode 100644
index 0000000..072e61f
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/serial.h
@@ -0,0 +1,131 @@
+/*
+ * linux/include/asm/arch-W90N745/serial.h
+ * 2003 winbond
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <asm/arch/hardware.h>
+#include <asm/irq.h>
+
+#define RS_TABLE_SIZE	1
+#define BASE_BAUD	115200
+#define STD_COM_FLAGS	(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_SERIAL_PORT_DEFNS		\
+	/* UART CLK PORT IRQ FLAGS */	\
+	{ 0, BASE_BAUD, UART_BASE0, INT_UARTINT, STD_COM_FLAGS },	/* ttyS0 */	
+#define EXTRA_SERIAL_PORT_DEFNS
+
+
+#define UART_LSR_OE	0x02		// Overrun error
+#define UART_LSR_PE	0x04		// Parity error
+#define UART_LSR_FE	0x08		// Frame error
+#define UART_LSR_BI	0x10		// Break detect
+//#define UART_LSR_DTR	0x10		// Data terminal ready
+#define UART_LSR_DR 0x01
+#define UART_LSR_THRE 0x20
+#define UART_IIR_DR	0x04		// Receive data ready
+#define UART_IIR_THRE	0x02		// Transmit buffer register empty
+#define UART_LSR_TEMT	0x40		// Transmit complete
+
+#define UART_LCR_WLEN5	0x00
+#define UART_LCR_WLEN6	0x01
+#define UART_LCR_WLEN7	0x02
+#define UART_LCR_WLEN8	0x03
+#define UART_LCR_PARITY	0x08
+#define UART_LCR_NPAR	0x00
+#define UART_LCR_OPAR	0x00
+#define UART_LCR_EPAR	0x10
+#define UART_LCR_SPAR	0x20
+#define UART_LCR_SBC	0x40
+#define UART_LCR_NSB	0x04
+
+#define UART_GCR_RX_INT	0x01
+#define UART_GCR_TX_INT	0x08
+#define UART_GCR_RX_STAT_INT	0x04
+
+#define UART_IER_RLSI	0x04
+#define UART_IER_THRI	0x02
+#define UART_IER_RDI	0x01
+	
+#define UART_MSR		0
+#define UART_MSR_DCD		0
+#define UART_MSR_RI		0
+#define UART_MSR_DSR		0
+#define UART_MSR_CTS		0
+#define UART_MSR_DDCD		0
+#define UART_MSR_TERI		0
+#define UART_MSR_DDSR		0
+#define UART_MSR_DCTS		0
+#define UART_MSR_ANY_DELTA	0
+
+#define PORT_W90N745	14
+
+struct serial_baudtable
+{
+	unsigned int baudrate;
+	unsigned int div;
+};
+
+static struct serial_baudtable uart_baudrate[] =
+{
+	{  1200, 0x30B},
+	{  2400, 0x184},
+	{  4800, 0xC1},
+	{  9600, 0x5F},
+	{ 19200, 0x2E},
+	{ 38400, 0x16},
+	{ 57600, 0x0E},
+	{115200, 0x06},
+	{230400, 0x02},
+	{460860, 0x00}
+};
+
+static unsigned int baudrate_div(unsigned int baudrate)
+{
+	int i;
+	int len = sizeof(uart_baudrate)/sizeof(struct serial_baudtable);
+	for(i = 0; i < len; i++)
+		if(uart_baudrate[i].baudrate == baudrate)
+			return uart_baudrate[i].div;
+	return 0;
+}
+
+#define disable_uart_tx_interrupt(line)		\
+{						\
+	if(line) {				\
+	}					\
+	else {					\
+		CSR_WRITE(COM_IER, CSR_READ(COM_IER)&0x1D);	\
+	}					\
+}
+
+#define disable_uart_rx_interrupt(line)		\
+{						\
+	if(line) {				\
+	}					\
+	else {					\
+		CSR_WRITE(COM_IER, CSR_READ(COM_IER)&0x1E);	\
+	}					\
+}
+
+#define enable_uart_tx_interrupt(line)		\
+{						\
+	if(line) {				\
+	}					\
+	else {					\
+		if(!(CSR_READ(COM_IER)&0x02))	\
+			CSR_WRITE(COM_IER, CSR_READ(COM_IER)|0x02);	\
+	}					\
+}
+
+#define enable_uart_rx_interrupt(line)		\
+{						\
+	if(line) {				\
+	}					\
+	else {					\
+		CSR_WRITE(COM_IER, CSR_READ(COM_IER)|0x1);	\
+	}					\
+}
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/shmparam.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/shmparam.h
new file mode 100644
index 0000000..073c7c2
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/shmparam.h
@@ -0,0 +1,5 @@
+/*
+ * linux/include/asm-arm/arch-a5k/shmparam.h
+ *
+ * Copyright (c) 1996 Russell King.
+ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/system.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/system.h
new file mode 100644
index 0000000..6c8d729
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/system.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-armnommu/arch-W90N745/system.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ * Copyright (c) 2001 RidgeRun, Inc (http://www.ridgerun.org)
+ *
+ */
+
+static inline void arch_idle(void)
+{
+	while (!current->need_resched && !hlt_counter);
+}
+
+extern inline void arch_reset(char mode)
+{
+	/* REVISIT --gmcnutt */
+}
+
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/time.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/time.h
new file mode 100644
index 0000000..4cbdc1a
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/time.h
@@ -0,0 +1,57 @@
+/*
+ * linux/include/asm/arch-W90N745/time.h
+ * 2003 winbond
+ */
+
+#ifndef __ASM_ARCH_TIME_H__
+#define __ASM_ARCH_TIME_H__
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/arch/timex.h>
+
+extern struct irqaction timer_irq;
+extern struct irqaction watchdog_irq;
+
+extern unsigned long winbond_gettimeoffset(void);
+extern void winbond_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+extern void winbond_watchdog_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+
+
+void __inline__ setup_timer (void)
+{
+
+	/*----- disable timer -----*/
+	CSR_WRITE(TCR0, 0);
+   	CSR_WRITE(TCR1, 0);
+   	
+	/* configure GPIO */
+	//CSR_WRITE(GPIO_CFG, 0x00150D0);//15AD8
+	CSR_WRITE(GPIO_CFG, 0x00050D0);//15AD8
+
+	CSR_WRITE (AIC_SCR13, 0x41);  /* high-level sensitive, priority level 1 */
+	/*----- timer 0 : periodic mode, 100 tick/sec -----*/
+	CSR_WRITE(TICR0, 0x5dc);//5dc//3a98->10//249f0//0xBB8->50//1d4c->20
+	//CSR_WRITE(TICR0, 0x4b0);//12M
+   
+	timer_irq.handler = winbond_timer_interrupt;
+	setup_arm_irq(IRQ_TIMER, &timer_irq);
+	
+	INT_ENABLE(IRQ_TIMER);
+		/*----- clear interrupt flag bit -----*/
+	CSR_WRITE(TISR, 0);  /* clear for safty */   
+
+	CSR_WRITE(TCR0, 0xe8000063);
+	
+#if 0//clyu 030616 //mcli
+	/*enable Watch dog*/
+	CSR_WRITE(WTCR, 0x01);/*reset timer*/
+	CSR_WRITE(WTCR, 0xF2);/*time-out=11*/
+	watchdog_irq.handler = winbond_watchdog_interrupt;
+	setup_arm_irq(INT_WDTINT, &watchdog_irq);
+#endif
+
+}
+
+#endif /* __ASM_ARCH_TIME_H__ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/timex.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/timex.h
new file mode 100644
index 0000000..0b814ca
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/timex.h
@@ -0,0 +1,12 @@
+/*
+ * timex.h:
+ * 2003 winbond
+ */
+#ifndef __ASM_ARCH_TIMEX_H__
+#define __ASM_ARCH_TIMEX_H__
+
+#include <asm/hardware.h>
+
+#define CLOCK_TICK_RATE	   (((fMCLK_MHz/100))*2)
+
+#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.c b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.c
new file mode 100644
index 0000000..02f7e36
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.c
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm/arch-W90N745/uncompress.c
+ * 2003 winbond
+ */
+
+#include <asm/hardware.h>
+
+static int s3c4510b_decomp_setup()
+{
+	CSR_WRITE(DEBUG_UARTLCON_BASE, DEBUG_ULCON_REG_VAL);
+	CSR_WRITE(DEBUG_UARTCONT_BASE, DEBUG_UCON_REG_VAL);
+	CSR_WRITE(DEBUG_UARTBRD_BASE,  DEBUG_UBRDIV_REG_VAL);
+}
+
+static int s3c4510b_putc(char c)
+{
+	CSR_WRITE(DEBUG_TX_BUFF_BASE, c);
+	while(!(CSR_READ(DEBUG_CHK_STAT_BASE) & DEBUG_TX_DONE_CHECK_BIT));
+
+	if(c == '\n')
+		s3c4510b_putc('\r');
+}
+
+static void s3c4510b_puts(const char *s)
+{
+	while(*s != '\0')
+		s3c4510b_putc(*s++);
+}
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.h
new file mode 100644
index 0000000..74ee0ad
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/uncompress.h
@@ -0,0 +1,50 @@
+/*
+ * asm/arch/uncompress.c:
+ *         Optional routines to aid in debugging the decompression phase
+ *         of kernel boot.
+ * copyright:
+ *         (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * author: Gordon McNutt <gmcnutt@ridgerun.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <asm/arch/uncompress.c>
+/*
+ * This is used by arch/armnommu/boot/compressed/misc.c to write progress info
+ * out the serial port so that the user can see debug messages up to the point
+ * where the kernel is decompressed. The STANDALONE_DEBUG macro chooses between
+ * this and the standard printf. Punt.
+ * --gmcnutt
+ */
+#define puts(s)			W90N745_puts(s)
+
+/*
+ * Not sure what this is for. Probably an optional watchdog to check if the
+ * decompress got hung so we can warn the user. Punt.
+ */
+#define arch_decomp_wdog()
+
+/*
+ * If we need to do some setup prior to decompression (like initializing the
+ * UART if we want to use puts() above) then we define it here. Punt.
+ */
+#define arch_decomp_setup()	W90N745_decomp_setup()
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/vmalloc.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/vmalloc.h
new file mode 100644
index 0000000..123c9bb
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/vmalloc.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-W90N745/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/wb_gdma.h b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/wb_gdma.h
new file mode 100644
index 0000000..f3a1698
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/arch-W90N745/wb_gdma.h
@@ -0,0 +1,669 @@
+/****************************************************************************
+ * 
+ * Copyright (c) 2004 - 2006 Winbond Electronics Corp. All rights reserved. 
+ *
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * 
+ * FILENAME
+ *    wb_gdma.h
+ *
+ * VERSION
+ *    1.0
+ *
+ * DESCRIPTION
+ *	  Winbond FA5933 GDMA driver header.  
+ *
+ * DATA STRUCTURES
+ *    None
+ *
+ * FUNCTIONS
+ *    None
+ *
+ * HISTORY
+ *    11/23/2006			Ver 1.0 Created by NS22 HHWu 
+ *
+ * REMARK
+ *    None
+ *
+ *************************************************************************/
+#ifndef _WB_FA5933_GDMA_H_
+#define _WB_FA5933_GDMA_H_
+
+#include <asm/irq.h>
+
+
+/* 12.22 add, NS22 HHWu */
+static wait_queue_head_t G0Wait, G1Wait;
+static volatile int nG0TXFinish, nG1TXFinish;
+
+/* if enable debug message, should take care the GDMA timing issue */
+//#define WB_DEBUG_GDMA
+
+#ifdef WB_DEBUG_GDMA
+#define WB_PRINTK_GDMA(fmt, arg...)		printk(fmt, ##arg)
+#else
+#define WB_PRINTK_GDMA(fmt, arg...)
+#endif 
+
+/* define struct GDMA_PARAM_T ucStatus */
+#define GDMA_INIT_OK		0x01
+#define GDMA_INT_OCCUR		0x02
+#define GDMA_INT_TERR		0x04  // GDMA transfer error
+
+/* define GDMA channel */
+#define GDMA0	0
+#define GDMA1	1
+
+/* define GDMA transfer mode */
+#define GDMA_nXDREQ_MODE		0x01 
+#define GDMA_DEMAND_MODE		0x02
+#define GDMA_SINGLE_MODE		0x04
+#define GDMA_BLOCK_MODE			0x08
+#define GDMA_BURST_MODE			0x10
+#define GDMA_SOFTWARE_MODE		0x20
+
+/* define GDMA nXDREQ & nXDACK */
+#define GDMA_REQ_ATV_HIGH		0x01
+#define GDMA_REQ_ATV_LOW		0x02  // default
+#define GDMA_ACK_ATV_HIGH		0x04
+#define GDMA_ACK_ATV_LOW		0x08  // default
+
+/* define GDMA SADIR & DADIR */
+#define GDMA_SADIR_INCREASE		0  // default
+#define GDMA_SADIR_DECREASE		1
+#define GDMA_DADIR_INCREASE		2  // default
+#define GDMA_DADIR_DECREASE		3
+
+/* define GDMA transfer width */
+#define GDMA_Bit8		0 
+#define GDMA_Bit16		1
+#define GDMA_Bit32		2
+
+#define gdma_outpw(port,value)     ( *( (unsigned volatile int *) port ) = value )
+#define gdma_inpw(port)            ( *( (unsigned volatile int *) port ) )
+
+/* define FA5933 EBI register */
+#define EBIBASEADDR				0xFFF01000
+#define FA5933_EBI_EXT3CON		(EBIBASEADDR + 0x0024)  // R/W
+
+/* define for FA5933_EBI_EXT3CON */
+#define EBI_ACS_0			0x0000
+#define EBI_ACS_1			0x0020
+#define EBI_ACS_2			0x0040
+#define EBI_ACS_3			0x0060
+#define EBI_ACS_4			0x0080
+#define EBI_ACS_5			0x00a0
+#define EBI_ACS_6			0x00c0
+#define EBI_ACS_7			0x00e0
+
+#define EBI_COS_0			0x0000
+#define EBI_COS_1			0x0004
+#define EBI_COS_2			0x0008
+#define EBI_COS_3			0x000c
+#define EBI_COS_4			0x0010
+#define EBI_COS_5			0x0014
+#define EBI_COS_6			0x0018
+#define EBI_COS_7			0x001c
+
+#define EBI_DBWD_8_BIT		0x01
+#define EBI_DBWD_16_BIT		0x02
+#define EBI_DBWD_32_BIT		0x03
+
+#define EBI_COH_0			0x0000
+#define EBI_COH_1			0x0100
+#define EBI_COH_2			0x0200
+#define EBI_COH_3			0x0300
+#define EBI_COH_4			0x0400
+#define EBI_COH_5			0x0500
+#define EBI_COH_6			0x0600
+#define EBI_COH_7			0x0700
+
+#define EBI_ACC_1			0x0800
+#define EBI_ACC_2			0x1000
+#define EBI_ACC_3			0x1800
+#define EBI_ACC_4			0x2000
+#define EBI_ACC_5			0x2800
+#define EBI_ACC_6			0x3000
+#define EBI_ACC_7			0x3800
+#define EBI_ACC_9			0x4000
+#define EBI_ACC_11			0x4800
+#define EBI_ACC_13			0x5000
+#define EBI_ACC_15			0x5800
+#define EBI_ACC_17			0x6000
+#define EBI_ACC_19			0x6800
+#define EBI_ACC_21			0x7000
+#define EBI_ACC_23			0x7800
+
+#define EBI_SIZE_256K		0x00000
+#define EBI_SIZE_512K		0x10000
+#define EBI_SIZE_1M			0x20000
+#define EBI_SIZE_2M			0x30000
+#define EBI_SIZE_4M			0x40000
+#define EBI_SIZE_8M			0x50000
+#define EBI_SIZE_16M		0x60000
+
+/* define FA5933 GPIO register */
+#define GPIOBASEADDR				0xFFF83000
+#define FA5933_GPIO_CFG1			(GPIOBASEADDR + 0x0010)  // R/W
+
+/* define FA5933 AIC register */
+#define AICBASEADDR				0xFFF82000
+#define FA5933_AIC19			(AICBASEADDR + 0x004C)
+#define FA5933_AIC_ISR			(AICBASEADDR + 0x0108)  // R
+#define FA5933_AIC_IPER			(AICBASEADDR + 0x010C)  // R
+#define FA5933_IMR				(AICBASEADDR + 0x0114)  // R
+#define FA5933_AIC_EOSCR		(AICBASEADDR + 0x0130)  // W
+#define FA5933_AIC_SCCR			(AICBASEADDR + 0x012C)  // W
+
+/* define FA5933 GDMA register */
+#define GDAMBASEADDR			0xFFF04000
+#define FA5933_GDMA_CTL0		(GDAMBASEADDR + 0x00)  // R/W 
+#define FA5933_GDMA_SRCB0		(GDAMBASEADDR + 0x04)  // R/W 
+#define FA5933_GDMA_DSTB0		(GDAMBASEADDR + 0x08)  // R/W 
+#define FA5933_GDMA_TCNT0		(GDAMBASEADDR + 0x0C)  // R/W 
+#define FA5933_GDMA_CSRC0		(GDAMBASEADDR + 0x10)  // R
+#define FA5933_GDMA_CDST0		(GDAMBASEADDR + 0x14)  // R
+#define FA5933_GDMA_CTCNT0		(GDAMBASEADDR + 0x18)  // R
+
+#define FA5933_GDMA_CTL1		(GDAMBASEADDR + 0x20)  // R/W 
+#define FA5933_GDMA_SRCB1		(GDAMBASEADDR + 0x24)  // R/W 
+#define FA5933_GDMA_DSTB1		(GDAMBASEADDR + 0x28)  // R/W 
+#define FA5933_GDMA_TCNT1		(GDAMBASEADDR + 0x2C)  // R/W 
+#define FA5933_GDMA_CSRC1		(GDAMBASEADDR + 0x30)  // R
+#define FA5933_GDMA_CDST1		(GDAMBASEADDR + 0x34)  // R
+#define FA5933_GDMA_CTCNT1		(GDAMBASEADDR + 0x38)  // R
+
+// define for FA5933_GDMA_CTL0/1
+#define GDMA_REQ_SEL_nXDREQ			(0x1 << 26)  // use nXDREQ
+#define GDMA_REQ_ATV				(0x1 << 25)  // nXDREQ is HIGH active			
+#define GDMA_ACK_ATV				(0x1 << 24)  // nXDACK is HIGH active		
+#define GDMA_SABNDERR				(0x1 << 22)  // R
+#define GDMA_DABNDERR				(0x1 << 21)  // R
+#define GDMA_GDMATERR				(0x1 << 20)  
+#define GDMA_AUTOIEN				(0x1 << 19) 
+#define GDMA_TC						(0x1 << 18)	  
+#define GDMA_BLOCK					(0x1 << 17)	
+#define GDMA_SOFTREQ				(0x1 << 16)
+#define GDMA_DM						(0x1 << 15)  // demand mode enable
+#define GDMA_TWS_8_Bit				(0x0 << 12)  // transfer width 8 bits
+#define GDMA_TWS_16_Bit				(0x1 << 12)  // transfer width 16 bits
+#define GDMA_TWS_32_Bit				(0x2 << 12)  // transfer width 32 bits
+#define GDMA_SBMS					(0x1 << 11)  // block mode
+#define GDMA_BME					(0x1 << 9)	 // burst mode
+#define GDMA_SIEN					(0x1 << 8)   
+#define GDMA_SAFIX					(0x1 << 7)
+#define GDMA_DAFIX					(0x1 << 6)
+#define GDMA_SADIR					(0x1 << 5)   // source address is decremented 
+#define GDMA_DADIR					(0x1 << 4)   // destination address is decremented 
+#define GDMA_GDMAMS_nXDREQ			(0x1 << 2)   // external nXDREQ mode for externa device 
+#define GDMA_GDMAEN					0x1
+
+/* define GDMA & EBI parameter structure  */
+// GDMA configure structure, defined for gdma_Init() 
+typedef void (GDMA_FUNC_T)(void);
+
+typedef struct FA5933_GDMA_PARAM{
+	unsigned char ucChannel;	// GDMA channel
+	unsigned char ucMode;
+	unsigned char ucWidth;
+	unsigned char ucReq;
+	unsigned char ucAck;
+	unsigned char ucSrcDir;
+	unsigned char ucDestDir;
+	
+	unsigned volatile char ucStatus[2];  // Note: volatile should before char or int	
+	GDMA_FUNC_T *fnGDMACallBack[2];  
+}GDMA_PARAM_T;
+
+// GDMA data transfer structure
+typedef struct FA5933_GDMA_DATA_TRANSFER{
+	unsigned char ucChannel;
+	unsigned int uSrcAddr;
+	unsigned int uDestAddr;
+	unsigned int uDataSize;
+}GDMA_DATA_T;
+
+// EBI cofnigure structure 
+typedef struct FA5933_EBI_PARAM{	
+	unsigned int uIOBaseAddr;	// EBI IO address
+	unsigned int uSize;
+	unsigned int uACC;
+	unsigned int uCOH;
+	unsigned int uACS;
+	unsigned int uCOS;
+	unsigned int uDBWD;
+}EBI_PARAM_T;
+
+/* define GDMA macro & inline functions */
+// Note: GDMA_SOFTREQ bit should be set with GDMA_GDMAEN at the same time
+#define gdma_Config_Transfer_Mode(ch, mode)\
+		{	unsigned volatile int val = 0;\
+			if(mode & GDMA_nXDREQ_MODE) val |= (GDMA_REQ_SEL_nXDREQ | GDMA_GDMAMS_nXDREQ);\
+		/*	if(mode & GDMA_SOFTWARE_MODE) val |= GDMA_SOFTREQ;*/ \
+			if(mode & GDMA_DEMAND_MODE) val |= GDMA_DM;\
+			if(mode & GDMA_BLOCK_MODE) val |= GDMA_SBMS;\
+			if(mode & GDMA_BURST_MODE) val |= GDMA_BME;\
+			WB_PRINTK_GDMA("GDMA: channel[%d] mode[0x%08x]\n", ch, val);\
+			if(ch == 0)	gdma_outpw(FA5933_GDMA_CTL0, val);\
+			if(ch == 1)	gdma_outpw(FA5933_GDMA_CTL1, val);\
+		}
+		
+#define gdma_Config_Transfer_Width(ch, width)\
+		{	unsigned volatile int val = 0;\
+			if(width == GDMA_Bit16) val = GDMA_TWS_16_Bit;\
+			if(width == GDMA_Bit32) val = GDMA_TWS_32_Bit;\
+			WB_PRINTK_GDMA("GDMA: channel[%d] widht[0x%08x]\n", ch, val);\
+			if(ch == 0)	gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) | val);\
+			if(ch == 1)	gdma_outpw(FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) | val);\
+		}		
+		
+#define gdma_Config_REQ_ACK_Active(ch, req, ack)\
+		{	unsigned volatile int val = 0;\
+			if(req == GDMA_REQ_ATV_HIGH) val |= GDMA_REQ_ATV;\
+			if(ack == GDMA_ACK_ATV_HIGH) val |= GDMA_ACK_ATV;\
+			WB_PRINTK_GDMA("GDMA: channel[%d] req_ack[0x%08x]\n", ch, val);\
+			if(ch == 0)	gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) | val);\
+			if(ch == 1)	gdma_outpw(FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) | val);\
+		}		
+		
+#define gdma_Conifg_SIEN(ch)\
+		if(ch == 0)	gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) | GDMA_SIEN);\
+		if(ch == 1)	gdma_outpw(FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) | GDMA_SIEN);\
+		
+#define gdma_Count_TCNT(ch, size)\
+		{	unsigned volatile int reg = 0, cnt = 0;\
+			if(ch == 0){ reg = (gdma_inpw(FA5933_GDMA_CTL0) & 0x3000) >> 12;\
+				if(reg == 0) cnt = size;\
+				if(reg == 1) cnt = size/2;\
+				if(reg == 2) cnt = size/4;\
+				if(gdma_inpw(FA5933_GDMA_CTL0) & GDMA_BME) cnt = cnt/4;\
+				gdma_outpw(FA5933_GDMA_TCNT0, cnt);\
+			}\
+			if(ch == 1){ reg = (gdma_inpw(FA5933_GDMA_CTL1) & 0x3000) >> 12;\
+				if(reg == 0) cnt = size;\
+				if(reg == 1) cnt = size/2;\
+				if(reg == 2) cnt = size/4;\
+				if(gdma_inpw(FA5933_GDMA_CTL1) & GDMA_BME) cnt = cnt/4;\
+				gdma_outpw(FA5933_GDMA_TCNT1, cnt);\
+			}\
+			/*WB_PRINTK_GDMA("GDMA: channel[%d] cnt[%d]\n", ch, cnt); // mark timing issue */ \
+		} 
+						
+#define gdma_Set_Source_Address(ch, src)\
+		{	if(ch == 0)	gdma_outpw(FA5933_GDMA_SRCB0, src | 0x80000000);\
+			if(ch == 1)	gdma_outpw(FA5933_GDMA_SRCB1, src  | 0x80000000);\
+			/*WB_PRINTK_GDMA("GDMA: ch[%d] src[0x%08x]\n", ch, src); // mark timing issue */  \
+		}
+		
+#define gdma_Set_Destination_Address(ch, dest)\
+		{	if(ch == 0)	gdma_outpw(FA5933_GDMA_DSTB0, dest | 0x80000000);\
+			if(ch == 1)	gdma_outpw(FA5933_GDMA_DSTB1, dest | 0x80000000);\
+			/*WB_PRINTK_GDMA("GDMA: ch[%d] dest[0x%08x]\n", ch, dest); // mark timing issue */ \
+		}
+		
+#define gdma_Config_ADDR_DIR(ch, sr, dr)\
+		{	unsigned volatile int reg = 0;\
+			if(sr == GDMA_SADIR_DECREASE) reg |= GDMA_SADIR;\
+			if(dr == GDMA_DADIR_DECREASE) reg |= GDMA_DADIR;\
+			if(ch == 0) gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) | reg);\
+			if(ch == 1) gdma_outpw(FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) | reg);\
+			WB_PRINTK_GDMA("GDMA: ch[%d] sadir[%d] dadir[%d]\n", ch, sr, dr);\
+		}		
+				
+
+//EBI_PARAM_T ebi_para;  
+GDMA_PARAM_T gdma_para;
+void gdma_Interrupt_Handler0(int irq, void *dev_id, struct pt_regs *regs);
+void gdma_Interrupt_Handler1(int irq, void *dev_id, struct pt_regs *regs);
+
+inline int gdma_Init(EBI_PARAM_T *pe, GDMA_PARAM_T *pg, GDMA_FUNC_T *pgfun) 
+{
+	unsigned volatile int uExt3Con, uReg;
+	
+	/* Configure FA5933 EBI */    
+	if(pe != 0)
+	{
+		uExt3Con = pe->uIOBaseAddr | pe->uSize | pe->uACC | pe->uCOH | pe->uACS | pe->uCOS | pe->uDBWD;
+		gdma_outpw(FA5933_EBI_EXT3CON, uExt3Con);
+		printk("EBI: EXT3CON[0x%08x]\n", gdma_inpw(FA5933_EBI_EXT3CON));
+	}		
+	
+	/* Configure FA5933 GDMA */
+	// step 1, check GDMA channel
+	if( (pg->ucChannel != 0) && (pg->ucChannel != 1) )
+	{
+		WB_PRINTK_GDMA("GDMA: channel error\n");
+		return -1;
+	}
+	
+	// Configure GPIO as nXDREQ & nXDACK    12.25 add, NS22 HHWu
+	uReg = gdma_inpw(FA5933_GPIO_CFG1);
+	uReg &= ~(0x0F);	
+	uReg |= 0x05;
+	gdma_outpw(FA5933_GPIO_CFG1, uReg);
+	
+	// initial GDMA struct, important
+	gdma_para.ucStatus[pg->ucChannel] = 0;  
+	gdma_para.fnGDMACallBack[pg->ucChannel] = 0;
+		
+	// step 2, configure transfer mode	
+	// Note: SINGLE_MODE & BLOCK_MODE are alternative. 	
+	// Note: nXDREQ_MODE & SOFTWARE_MODE are alternative. 
+	if( (pg->ucMode & GDMA_SINGLE_MODE) && (pg->ucMode & GDMA_BLOCK_MODE) )	
+	{
+		WB_PRINTK_GDMA("GDMA: single & block mode are alternative\n");
+		return -2;
+	}	
+	if( (pg->ucMode & GDMA_nXDREQ_MODE) && (pg->ucMode & GDMA_SOFTWARE_MODE) )
+	{	
+		WB_PRINTK_GDMA("GDMA: XDREQ & software mode are alternative\n");	
+		return -3;	
+	}		
+	gdma_Config_Transfer_Mode(pg->ucChannel, pg->ucMode);	
+	
+	// step 3, configure transfer width
+	if( (pg->ucWidth != GDMA_Bit8) && (pg->ucWidth != GDMA_Bit16) && (pg->ucWidth != GDMA_Bit32) )
+	{
+		WB_PRINTK_GDMA("GDMA: transfer width error\n");
+		return -4;
+	}		
+	gdma_Config_Transfer_Width(pg->ucChannel, pg->ucWidth);	
+	
+	// step 4, configure nXDREQ & nXDACK active
+	if( (pg->ucReq != GDMA_REQ_ATV_HIGH) && (pg->ucReq != GDMA_REQ_ATV_LOW) )
+	{
+		WB_PRINTK_GDMA("GDMA: nXDREQ active error\n");
+		return -5;
+	}
+	if( (pg->ucAck != GDMA_ACK_ATV_HIGH) && (pg->ucAck != GDMA_ACK_ATV_LOW) )
+	{
+		WB_PRINTK_GDMA("GDMA: nXDACK active error\n");
+		return -6;
+	}	
+	gdma_Config_REQ_ACK_Active(pg->ucChannel, pg->ucReq, pg->ucAck);
+
+	// step 5, configure SIEN
+	gdma_Conifg_SIEN(pg->ucChannel);
+	
+	// step 6, configure SADIR DADIR 
+	if( (pg->ucSrcDir != GDMA_SADIR_INCREASE) && (pg->ucSrcDir != GDMA_SADIR_DECREASE) )
+	{
+		WB_PRINTK_GDMA("GDMA: source address direction error\n");
+		return -7;
+	}
+	if( (pg->ucDestDir != GDMA_DADIR_INCREASE) && (pg->ucDestDir != GDMA_DADIR_DECREASE) )
+	{
+		WB_PRINTK_GDMA("GDMA: destination address direction error\n");
+		return -8;
+	}
+	gdma_Config_ADDR_DIR(pg->ucChannel, pg->ucSrcDir, pg->ucDestDir);
+	
+	// step 7, install GDMA ISR and call back function ..... call back function param issue not yet
+	if(pg->ucChannel == 0)
+	{
+		if(pgfun != 0)
+			gdma_para.fnGDMACallBack[0] = pgfun;	
+		
+		if(request_irq(19, gdma_Interrupt_Handler0,  SA_INTERRUPT, "wbgdma0", 0)) 
+		{
+			WB_PRINTK_GDMA("GDMA: install GDMA ISR 0 fail\n");
+			return -9;
+		}	
+		else
+		{	
+			WB_PRINTK_GDMA("GDMA: install GDMA ISR 0 success\n");
+			enable_irq(19);
+		}
+
+// HHWu adde    12.22 add.		
+		init_waitqueue_head(&G0Wait);	
+// HHWu adde			
+	}
+	else
+	{
+		if(pgfun != 0)
+			gdma_para.fnGDMACallBack[1] = pgfun;	
+		
+		if(request_irq(20, gdma_Interrupt_Handler1,  SA_INTERRUPT, "wbgdma1", 0)) 
+		{
+			WB_PRINTK_GDMA("GDMA: install GDMA ISR 1 fail\n");
+			return -10;
+		}	
+		else
+		{	
+			WB_PRINTK_GDMA("GDMA: install GDMA ISR 1 success\n");
+			enable_irq(20);
+		}
+		
+// HHWu adde    12.22 add.		
+		init_waitqueue_head(&G1Wait);	
+// HHWu adde		
+	}
+	
+	if(pg->ucChannel == 0)
+		WB_PRINTK_GDMA("GDMA: gdma_Init ch[%d] CTL[0x%08x]\n", pg->ucChannel, gdma_inpw(FA5933_GDMA_CTL0));
+	else
+		WB_PRINTK_GDMA("GDMA: gdma_Init ch[%d] CTL[0x%08x]\n", pg->ucChannel, gdma_inpw(FA5933_GDMA_CTL1));	
+
+	gdma_para.ucStatus[pg->ucChannel] |= GDMA_INIT_OK;
+	return 0;  // success	
+}	
+
+inline void gdma_Release(GDMA_PARAM_T *pg)
+{
+	if(pg->ucChannel == 0)
+		free_irq(19, 0);  // 2nd parameter ..... not yet
+	if(pg->ucChannel == 1)
+		free_irq(20, 0);  // 2nd parameter ..... not yet
+}	
+
+inline int gdma_IO_To_Memory(GDMA_DATA_T *pd)  // set GDMA_SAFIX
+{
+	// should check initial specific GDMA channel before 
+	if( !(gdma_para.ucStatus[pd->ucChannel] & GDMA_INIT_OK) )
+	{
+		WB_PRINTK_GDMA("GDMA: gdma_IO_To_Memory GDMA[%d] not initial\n", pd->ucChannel);
+		return -1;	
+	}
+	
+	gdma_Count_TCNT(pd->ucChannel, pd->uDataSize);
+	gdma_Set_Source_Address(pd->ucChannel, pd->uSrcAddr);
+	gdma_Set_Destination_Address(pd->ucChannel, pd->uDestAddr);
+	
+	switch(pd->ucChannel)
+	{
+		case 0:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL0) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_IO_To_Memory GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL0));  
+				return -2;	
+			}	
+			
+// HHWu adde    12.22 modify.			
+			nG0TXFinish = 0;
+			gdma_outpw( FA5933_GDMA_CTL0, (gdma_inpw(FA5933_GDMA_CTL0) | GDMA_SAFIX | GDMA_GDMAEN) );
+			wait_event_interruptible(G0Wait, nG0TXFinish != 0);
+// HHWu adde			
+			break;
+			
+		case 1:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL1) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_IO_To_Memory GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL1));  
+				return -3;	
+			}
+			
+// HHWu adde    12.22 modify.			
+			nG1TXFinish = 0;
+			gdma_outpw( FA5933_GDMA_CTL1, (gdma_inpw(FA5933_GDMA_CTL1) | GDMA_SAFIX | GDMA_GDMAEN) );
+			wait_event_interruptible(G1Wait, nG1TXFinish != 0);
+// HHWu adde			
+			break;
+			
+		default:
+			WB_PRINTK_GDMA("GDMA: gdma_IO_To_Memory channel error\n");
+			return -4;	
+	}	
+	return 0;  // success	
+}
+
+inline int gdma_Memory_To_IO(GDMA_DATA_T *pd)  // set GDMA_DAFIX
+{
+	// should check initial specific GDMA channel before 
+	if( !(gdma_para.ucStatus[pd->ucChannel] & GDMA_INIT_OK) )
+	{
+		WB_PRINTK_GDMA("GDMA: gdma_Memory_To_IO GDMA[%d] not initial\n", pd->ucChannel);
+		return -1;	
+	}
+	
+	gdma_Count_TCNT(pd->ucChannel, pd->uDataSize);
+	gdma_Set_Source_Address(pd->ucChannel, pd->uSrcAddr);
+	gdma_Set_Destination_Address(pd->ucChannel, pd->uDestAddr);
+	
+	switch(pd->ucChannel)
+	{
+		case 0:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL0) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_Memory_To_IO GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL0));  
+				return -2;	
+			}
+			
+// HHWu adde    12.22 modify.			
+			nG0TXFinish = 0;
+			gdma_outpw( FA5933_GDMA_CTL0, (gdma_inpw(FA5933_GDMA_CTL0) | GDMA_DAFIX | GDMA_GDMAEN) );
+			wait_event_interruptible(G0Wait, nG0TXFinish != 0);
+// HHWu adde			
+			break;
+			
+		case 1:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL1) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_Memory_To_IO GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL1));  
+				return -3;	
+			}
+			
+// HHWu adde    12.22 modify.			
+			nG1TXFinish = 0;
+			gdma_outpw( FA5933_GDMA_CTL1, (gdma_inpw(FA5933_GDMA_CTL1) | GDMA_DAFIX | GDMA_GDMAEN) );
+			wait_event_interruptible(G1Wait, nG1TXFinish != 0);
+// HHWu adde			
+			break;
+			
+		default:
+			WB_PRINTK_GDMA("GDMA: gdma_Memory_To_IO channel error\n");
+			return -4;	
+	}	
+	return 0;  // success	
+}
+
+inline int gdma_Memory_To_Memory(GDMA_DATA_T *pd)  // don't set GDMA_DAFIX & GDMA_SAFIX, set GDMA_SOFTREQ
+{
+	// should check initial specific GDMA channel before 
+	if( !(gdma_para.ucStatus[pd->ucChannel] & GDMA_INIT_OK) )
+	{
+		WB_PRINTK_GDMA("GDMA: gdma_Memory_To_Memory GDMA[%d] not initial\n", pd->ucChannel);
+		return -1;	
+	}
+	
+	gdma_Count_TCNT(pd->ucChannel, pd->uDataSize);
+	gdma_Set_Source_Address(pd->ucChannel, pd->uSrcAddr);
+	gdma_Set_Destination_Address(pd->ucChannel, pd->uDestAddr);
+	
+	switch(pd->ucChannel)
+	{
+		case 0:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL0) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_Memory_To_Memory GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL0)); 
+				return -2;	
+			}
+			
+// HHWu adde    12.22 modify.			
+			nG0TXFinish = 0;
+			gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) | GDMA_SOFTREQ | GDMA_GDMAEN);
+			wait_event_interruptible(G0Wait, nG0TXFinish != 0);
+// HHWu adde			
+			break;
+			
+		case 1:
+			// should check SABNDERR & DABNDERR bit, TWS have to set in gdma_Init() before
+			if(gdma_inpw(FA5933_GDMA_CTL1) & 0x600000)
+			{
+				WB_PRINTK_GDMA("GDMA: gdma_Memory_To_Memory GDMA[%d] address boundary error[0x%08x]\n", 
+					pd->ucChannel, gdma_inpw(FA5933_GDMA_CTL1)); 
+				return -3;	
+			}
+			
+// HHWu adde    12.22 modify.			
+			nG1TXFinish = 0;
+			gdma_outpw( FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) | GDMA_SOFTREQ | GDMA_GDMAEN);
+			wait_event_interruptible(G1Wait, nG1TXFinish != 0);
+// HHWu adde				
+			break;
+			
+		default:
+			WB_PRINTK_GDMA("GDMA: gdma_Memory_To_Memory channel error\n");
+			return -4;	
+	}	
+	return 0;  // success	
+}
+
+void gdma_Interrupt_Handler0(int irq, void *dev_id, struct pt_regs *regs)
+{
+	WB_PRINTK_GDMA("GDMA: INT0\n");  
+	
+	// interrupt occured continuously, TC be set & AIC IPER is 0 ..... strange	
+	gdma_outpw(FA5933_AIC_SCCR, 1 << 19);
+	gdma_outpw(FA5933_GDMA_CTL0, gdma_inpw(FA5933_GDMA_CTL0) & (~GDMA_TC));  // clear by write 0
+	
+	// maintain GDMA status ..... GDMATERR not yet 
+	gdma_para.ucStatus[0] |= GDMA_INT_OCCUR;
+		
+	// execute back function 
+	if(gdma_para.fnGDMACallBack[0] != 0)
+		gdma_para.fnGDMACallBack[0](); 
+		
+// HHWu addb    12.22 add
+	nG0TXFinish = 1;
+	wake_up_interruptible(&G0Wait);
+	return;
+// HHWu adde		 
+}
+ 
+void gdma_Interrupt_Handler1(int irq, void *dev_id, struct pt_regs *regs)
+{
+	WB_PRINTK_GDMA("GDMA: INT1\n");  
+	
+	// interrupt occured continuously, TC be set & AIC IPER is 0 ..... strange	
+	gdma_outpw(FA5933_AIC_SCCR, 1 << 20);
+	gdma_outpw(FA5933_GDMA_CTL1, gdma_inpw(FA5933_GDMA_CTL1) & (~GDMA_TC));  // clear by write 0
+	
+	// maintain GDMA status ..... GDMATERR not yet 
+	gdma_para.ucStatus[1] |= GDMA_INT_OCCUR;
+	
+	// execute back function 
+	if(gdma_para.fnGDMACallBack[1] != 0)
+		gdma_para.fnGDMACallBack[1]();
+		
+// HHWu addb    12.22 add
+	nG1TXFinish = 1;
+	wake_up_interruptible(&G1Wait);
+// HHWu adde			  
+} 
+ 
+ 
+#endif 
+ 
\ No newline at end of file
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/io.h b/uClinux-2.4.20-uc1/include/asm-armnommu/io.h
index d89a815..397ae7c 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/io.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/io.h
@@ -202,6 +202,10 @@ extern void __readwrite_bug(const char *fn);
  * macros.  These should only be used with the cookie passed from
  * ioremap.
  */
+#ifdef CONFIG_ARCH_WINBOND
+#define __mem_pci(c) (c)
+#endif
+
 #ifdef __mem_pci
 
 #ifdef __io_noswap
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/mc146818rtc.h b/uClinux-2.4.20-uc1/include/asm-armnommu/mc146818rtc.h
index 7b81e0c..697dfa3 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/mc146818rtc.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/mc146818rtc.h
@@ -7,9 +7,11 @@
 #include <asm/arch/irqs.h>
 #include <asm/io.h>
 
+#include <linux/w83977.h>
+
 #ifndef RTC_PORT
-#define RTC_PORT(x)	(0x70 + (x))
-#define RTC_ALWAYS_BCD	1	/* RTC operates in binary mode */
+#define RTC_PORT(x)	(W83977AF_BASE + 0x70 + (x))
+#define RTC_ALWAYS_BCD	0	/* RTC operates in binary mode */
 #endif
 
 /*
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/pci.h b/uClinux-2.4.20-uc1/include/asm-armnommu/pci.h
index 0bf0c26..d998b44 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/pci.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/pci.h
@@ -151,6 +151,10 @@ extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
 /* Return the index of the PCI controller for device PDEV. */
 #define pci_controller_num(PDEV)	(0)
 
+#ifdef CONFIG_BOARD_W90N745
+#define PCI_DMA_BUS_IS_PHYS	(1)
+#endif
+
 #endif /* __KERNEL__ */
  
 #endif
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/proc-armv/cache.h b/uClinux-2.4.20-uc1/include/asm-armnommu/proc-armv/cache.h
index 5f23fd4..64dae42 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/proc-armv/cache.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/proc-armv/cache.h
@@ -24,6 +24,11 @@
 /*
  * Generic I + D cache
  */
+ 
+extern EnableCache();
+extern void DisableCache();
+extern void FlushCache();
+
 #define flush_cache_all()						\
 	do {								\
 		cpu_cache_clean_invalidate_all();			\
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/types.h b/uClinux-2.4.20-uc1/include/asm-armnommu/types.h
index 39d5290..398c5da 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/types.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/types.h
@@ -17,6 +17,10 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
+#ifdef CONFIG_BOARD_W90N745
+typedef __u32 dma64_addr_t;
+#endif
+
 #if defined(__GNUC__) && !defined(__STRICT_ANSI__)
 typedef __signed__ long long __s64;
 typedef unsigned long long __u64;
diff --git a/uClinux-2.4.20-uc1/include/asm-armnommu/unistd.h b/uClinux-2.4.20-uc1/include/asm-armnommu/unistd.h
index af756fd..b2b99ad 100644
--- a/uClinux-2.4.20-uc1/include/asm-armnommu/unistd.h
+++ b/uClinux-2.4.20-uc1/include/asm-armnommu/unistd.h
@@ -243,6 +243,14 @@
 #define __NR_mincore			(__NR_SYSCALL_BASE+219)
 #define __NR_madvise			(__NR_SYSCALL_BASE+220)
 #define __NR_fcntl64			(__NR_SYSCALL_BASE+221)
+#define __NR_FindImage			(__NR_SYSCALL_BASE+222)
+#define __NR_DelImage			(__NR_SYSCALL_BASE+223)
+#define __NR_CorruptCheck		(__NR_SYSCALL_BASE+224)
+#define __NR_ReadWinbondFlash		(__NR_SYSCALL_BASE+225)
+#define __NR_WriteWinbondFlash		(__NR_SYSCALL_BASE+226)
+
+#define __NR_GPIO_I2C_Byte_Xfer		(__NR_SYSCALL_BASE+231)
+#define __NR_GPIO_SPI_Send_Byte		(__NR_SYSCALL_BASE+232)
 
 /*
  * The following SWIs are ARM private.
diff --git a/uClinux-2.4.20-uc1/include/linux/interrupt.h b/uClinux-2.4.20-uc1/include/linux/interrupt.h
index d2afbde..4200c78 100644
--- a/uClinux-2.4.20-uc1/include/linux/interrupt.h
+++ b/uClinux-2.4.20-uc1/include/linux/interrupt.h
@@ -39,7 +39,8 @@ enum {
 	CM206_BH,
 	JS_BH,
 	MACSERIAL_BH,
-	ISICOM_BH
+	ISICOM_BH,
+	SERIAL83977_BH
 };
 
 #include <asm/hardirq.h>
diff --git a/uClinux-2.4.20-uc1/include/linux/w83977.h b/uClinux-2.4.20-uc1/include/linux/w83977.h
new file mode 100644
index 0000000..f6fee8b
--- /dev/null
+++ b/uClinux-2.4.20-uc1/include/linux/w83977.h
@@ -0,0 +1,147 @@
+/****************************************************************************
+ *                                                                                                                           *
+ * Copyright (c) 2004 - 2006 Winbond Electronics Corp. All rights reserved.                          *
+ *                                                                                                                           *
+ ***************************************************************************/
+ 
+/****************************************************************************
+ * 
+ * FILENAME
+ *     linux-2.4.x/include/linux/w83977.h
+ *
+ * VERSION
+ *     1.0
+ *
+ * DESCRIPTION
+ *     This is the head file of W83977AF
+ *
+ * DATA STRUCTURES
+ *     None
+ *
+ * FUNCTIONS
+ *     None
+ *
+ * HISTORY
+ *     13/2/2004		 Ver 1.0 Created by PC34 MCLi
+ *
+ * REMARK
+ *     None
+ * MODIFY
+ *	  16/11/2004	by PC34 MCLi
+ *	  	Delete the W83977EF driver codes
+ **************************************************************************/
+
+#ifndef __W83977_H_
+#define __W83977_H_
+
+#include <asm/arch/hardware.h>
+
+#define VPint   			*(volatile unsigned int *)
+#define VPshort 			*(volatile unsigned short *)
+#define VPchar  			*(volatile unsigned char *)
+
+#define outdw(r,v)		(VPint(r)=(v))
+#define indw(r)			(VPint(r))
+
+/* W83977AF UART Ports */
+#ifndef UART_PORTA
+#define UART_PORTA 2
+#endif
+
+#ifndef UART_PORTB
+#define UART_PORTB 3
+#endif
+
+#ifndef UART_PORTC
+#define UART_PORTC 6
+#endif
+
+#define PORT_W83977	        15
+#define PORT_REF_CLOCK		1846100 /* 1.8461MHZ */
+
+#define W83977_BASE (W83977AF_BASE_ADDR|0x80000000)
+#define W83977AF_BASE W83977_BASE
+
+#define PARA_BASE W83977_BASE+0x378
+
+/* W83977 Default UART base address */
+#define UART_BASEA	W83977_BASE+0x3F8
+#define UART_BASEB	W83977_BASE+0x2F8
+#define UART_BASEC	W83977_BASE+0x4F8
+
+/* UART A */
+#define PORTA_RBR	UART_BASEA + 0		/* R */
+#define PORTA_TBR	UART_BASEA + 0		/* W */
+#define PORTA_ICR	UART_BASEA + 1		/* R & W */
+#define PORTA_ISR	UART_BASEA + 2		/* R */
+#define PORTA_UFR	UART_BASEA + 2		/* W */
+#define PORTA_UCR	UART_BASEA + 3		/* R & W */
+#define PORTA_HCR	UART_BASEA + 4		/* R & W */
+#define PORTA_USR	UART_BASEA + 5		/* R & W */
+#define PORTA_HSR	UART_BASEA + 6		/* R & W */
+#define PORTA_UDR	UART_BASEA + 7		/* R & W */
+#define PORTA_BLL	UART_BASEA + 0		/* R & W */
+#define PORTA_BLH	UART_BASEA + 1		/* R & W */
+
+/* UART B */
+#define PORTB_RBR	UART_BASEB + 0		/* R */
+#define PORTB_TBR	UART_BASEB + 0		/* W */
+#define PORTB_ICR	UART_BASEB + 1		/* R & W */
+#define PORTB_ISR	UART_BASEB + 2		/* R */
+#define PORTB_UFR	UART_BASEB + 2		/* W */
+#define PORTB_UCR	UART_BASEB + 3		/* R & W */
+#define PORTB_HCR	UART_BASEB + 4		/* R & W */
+#define PORTB_USR	UART_BASEB + 5		/* R & W */
+#define PORTB_HSR	UART_BASEB + 6		/* R & W */
+#define PORTB_UDR	UART_BASEB + 7		/* R & W */
+#define PORTB_BLL	UART_BASEB + 0		/* R & W */
+#define PORTB_BLH	UART_BASEB + 1		/* R & W */
+
+/* UART C */
+#define PORTC_RBR	UART_BASEC + 0		/* R */
+#define PORTC_TBR	UART_BASEC + 0		/* W */
+#define PORTC_ICR	UART_BASEC + 1		/* R & W */
+#define PORTC_ISR	UART_BASEC + 2		/* R */
+#define PORTC_UFR	UART_BASEC + 2		/* W */
+#define PORTC_ADCR1	UART_BASEC + 2		/* R & W */
+#define PORTC_UCR	UART_BASEC + 3		/* R & W */
+#define PORTC_HCR	UART_BASEC + 4		/* R & W */
+#define PORTC_ADCR2	UART_BASEC + 4		/* R & W */
+#define PORTC_USR	UART_BASEC + 5		/* R & W */
+#define PORTC_HSR	UART_BASEC + 6		/* R & W */
+#define PORTC_UDR	UART_BASEC + 7		/* R & W */
+#define PORTC_BLL	UART_BASEC + 0		/* R & W */
+#define PORTC_BLH	UART_BASEC + 1		/* R & W */
+
+/* Configuration port and key */
+#define AF_CONFIG_PORT		W83977_BASE+0x3f0
+#define AF_INDEX_PORT		AF_CONFIG_PORT
+#define AF_DATA_PORT		W83977_BASE+0x3f1
+
+/* Compatible PnP registers */
+#define EFER_REG	0x3F0         /* Extended Function Enable Register */
+#define EFIR_REG	EFER_REG      /* Extended Function Index Register */
+#define EFDR_REG	(EFER_REG+1)  /* Extended Function Data Register */
+
+#define CR20		0x20
+#define CR21		0x21
+
+#define KBC_DEV				5	/* logical device 5 */
+
+/* W83977 definitions */
+#define W83977AF_DEV_ID		0x97     /* device ID */
+#define W83977AF_DEV_REV	0x77     /* revision ID */
+#define W83977EF_DEV_ID		0x52     /* device ID */
+#define W83977EF_DEV_REV	0xF6	 /* device ID */
+
+/* I/O registers */
+#define KBC_STATUS_REG		*((volatile unsigned char *) (W83977_BASE + 0x64))  /* input */
+#define KBC_COMMAND_REG		*((volatile unsigned char *) (W83977_BASE + 0x64))  /* output */
+#define KBC_OUTBUF_REG		*((volatile unsigned char *) (W83977_BASE + 0x60))  /* output */
+#define KBC_DATA_REG			*((volatile unsigned char *) (W83977_BASE + 0x60))  /* input */
+
+#define KBC_INPUT_BUF_FULL	0x02
+#define KBC_OUTPUT_BUF_FULL	0x01
+
+
+#endif