From 936b58fc261c4f4e19046b34cac0da7e64591b54 Mon Sep 17 00:00:00 2001 From: Oliver Schinagl Date: Tue, 12 Apr 2011 06:51:10 +0000 Subject: Changes to support the w90n745 serial ports. Should very probably be moved to seperate files. --- uClinux-2.4.20-uc1/include/linux/serial.h | 7 ++ uClinux-2.4.20-uc1/include/linux/serial_reg.h | 169 ++++++++++++++++++++++++-- 2 files changed, 163 insertions(+), 13 deletions(-) diff --git a/uClinux-2.4.20-uc1/include/linux/serial.h b/uClinux-2.4.20-uc1/include/linux/serial.h index fa4b807..f7243fa 100644 --- a/uClinux-2.4.20-uc1/include/linux/serial.h +++ b/uClinux-2.4.20-uc1/include/linux/serial.h @@ -10,6 +10,13 @@ #ifndef _LINUX_SERIAL_H #define _LINUX_SERIAL_H +#include +#include + +#define RS_TABLE_SIZE 5 +#define BASE_BAUD 115200 +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + #ifdef __KERNEL__ #include diff --git a/uClinux-2.4.20-uc1/include/linux/serial_reg.h b/uClinux-2.4.20-uc1/include/linux/serial_reg.h index cc362b7..1253bf8 100644 --- a/uClinux-2.4.20-uc1/include/linux/serial_reg.h +++ b/uClinux-2.4.20-uc1/include/linux/serial_reg.h @@ -22,25 +22,168 @@ * Out: Fifo custom trigger levels * XR16C85x only */ -#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ -#define UART_IER 1 /* Out: Interrupt Enable Register */ -#define UART_FCTR 1 /* (LCR=BF) Feature Control Register +#define UART_DLM 0x04 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 0x04 /* Out: Interrupt Enable Register */ +#define UART_FCTR 0x04 /* (LCR=BF) Feature Control Register * XR16C85x only */ -#define UART_IIR 2 /* In: Interrupt ID Register */ -#define UART_FCR 2 /* Out: FIFO Control Register */ -#define UART_EFR 2 /* I/O: Extended Features Register */ +#define UART_IIR 0x08 /* In: Interrupt ID Register */ +#define UART_FCR 0x08 /* Out: FIFO Control Register */ +#define UART_EFR 0x08 /* I/O: Extended Features Register */ /* (DLAB=1, 16C660 only) */ - -#define UART_LCR 3 /* Out: Line Control Register */ -#define UART_MCR 4 /* Out: Modem Control Register */ -#define UART_LSR 5 /* In: Line Status Register */ -#define UART_MSR 6 /* In: Modem Status Register */ -#define UART_SCR 7 /* I/O: Scratch Register */ -#define UART_EMSR 7 /* (LCR=BF) Extended Mode Select Register +#define UART_ADCR1 0x08 + +#define UART_LCR 0x0C /* Out: Line Control Register */ +#define UART_MCR 0x10 /* Out: Modem Control Register */ +#define UART_LSR 0x14 /* In: Line Status Register */ +#define UART_MSR 0x18 /* In: Modem Status Register */ +#define UART_SCR 0x1C /* I/O: Scratch Register */ +#define UART_EMSR 0x1C /* (LCR=BF) Extended Mode Select Register * FCTR bit 6 selects SCR or EMSR * XR16c85x only */ +#define COM_TX_1 (UART_BASE1+0x00) +#define COM_RX_1 (UART_BASE1+0x00) +#define COM_DLL_1 (UART_BASE1+0x00) +#define COM_DLM_1 (UART_BASE1+0x04) +#define COM_IER_1 (UART_BASE1+0x04) +#define COM_IIR_1 (UART_BASE1+0x08) +#define COM_FCR_1 (UART_BASE1+0x08) +#define COM_LCR_1 (UART_BASE1+0x0c) +#define COM_MCR_1 (UART_BASE1+0x10) +#define COM_LSR_1 (UART_BASE1+0x14) +#define COM_MSR_1 (UART_BASE1+0x18) +#define COM_TOR_1 (UART_BASE1+0x1c) + +#define COM_TX_2 (UART_BASE2+0x00) +#define COM_RX_2 (UART_BASE2+0x00) +#define COM_DLL_2 (UART_BASE2+0x00) +#define COM_DLM_2 (UART_BASE2+0x04) +#define COM_IER_2 (UART_BASE2+0x04) +#define COM_IIR_2 (UART_BASE2+0x08) +#define COM_FCR_2 (UART_BASE2+0x08) +#define COM_LCR_2 (UART_BASE2+0x0c) +#define COM_MCR_2 (UART_BASE2+0x10) +#define COM_LSR_2 (UART_BASE2+0x14) +#define COM_MSR_2 (UART_BASE2+0x18) +#define COM_TOR_2 (UART_BASE2+0x1c) + +#define COM_TX_3 (UART_BASE3+0x00) +#define COM_RX_3 (UART_BASE3+0x00) +#define COM_DLL_3 (UART_BASE3+0x00) +#define COM_DLM_3 (UART_BASE3+0x04) +#define COM_IER_3 (UART_BASE3+0x04) +#define COM_IIR_3 (UART_BASE3+0x08) +#define COM_FCR_3 (UART_BASE3+0x08) +#define COM_LCR_3 (UART_BASE3+0x0c) +#define COM_MCR_3 (UART_BASE3+0x10) +#define COM_LSR_3 (UART_BASE3+0x14) +#define COM_MSR_3 (UART_BASE3+0x18) +#define COM_TOR_3 (UART_BASE3+0x1c) + +#define disable_uart_tx_interrupt_1(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_1, CSR_READ(COM_IER_1)&0x1D); \ + } \ +} + +#define disable_uart_rx_interrupt_1(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_1, CSR_READ(COM_IER_1)&0x1E); \ + } \ +} + +#define enable_uart_tx_interrupt_1(line) \ +{ \ + if(line) { \ + } else { \ + if(!(CSR_READ(COM_IER_1)&0x02)) { \ + CSR_WRITE(COM_IER_1, CSR_READ(COM_IER_1)|0x02); \ + } \ + } \ +} + +#define enable_uart_rx_interrupt_1(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_1, CSR_READ(COM_IER_1)|0x1); \ + } \ +} + + +#define disable_uart_tx_interrupt_2(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_2, CSR_READ(COM_IER_2)&0x1D); \ + } \ +} + +#define disable_uart_rx_interrupt_2(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_2, CSR_READ(COM_IER_2)&0x1E); \ + } \ +} + +#define enable_uart_tx_interrupt_2(line) \ +{ \ + if(line) { \ + } else { \ + if(!(CSR_READ(COM_IER_2)&0x02)) \ + CSR_WRITE(COM_IER_2, CSR_READ(COM_IER_2)|0x02); \ + } \ +} + +#define enable_uart_rx_interrupt_2(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_2, CSR_READ(COM_IER_2)|0x1); \ + } \ +} + + +#define disable_uart_tx_interrupt_3(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_3, CSR_READ(COM_IER_3)&0x1D); \ + } \ +} + +#define disable_uart_rx_interrupt_3(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_3, CSR_READ(COM_IER_3)&0x1E); \ + } \ +} + +#define enable_uart_tx_interrupt_3(line) \ +{ \ + if(line) { \ + } else { \ + if(!(CSR_READ(COM_IER_3)&0x02)) { \ + CSR_WRITE(COM_IER_3, CSR_READ(COM_IER_3)|0x02); \ + } \ + } \ +} + +#define enable_uart_rx_interrupt_3(line) \ +{ \ + if(line) { \ + } else { \ + CSR_WRITE(COM_IER_3, CSR_READ(COM_IER_3)|0x1); \ + } \ +} + /* * These are the definitions for the FIFO Control Register * (16650 only) -- cgit v0.12