diff options
Diffstat (limited to 'v4l/kernel-2.6.tmp/usb_biu_reg.h')
| -rw-r--r-- | v4l/kernel-2.6.tmp/usb_biu_reg.h | 557 |
1 files changed, 557 insertions, 0 deletions
diff --git a/v4l/kernel-2.6.tmp/usb_biu_reg.h b/v4l/kernel-2.6.tmp/usb_biu_reg.h new file mode 100644 index 0000000..6811466 --- /dev/null +++ b/v4l/kernel-2.6.tmp/usb_biu_reg.h @@ -0,0 +1,557 @@ +// biu_reg.h 1-9-2006 +// gen_biu Ver 1.9 generated by luke +#define xd_p_reg_usb_cfg_speed ( 0xDD00) +#define p_reg_usb_cfg_speed 0xDD00 +#define reg_usb_cfg_speed_pos 0 +#define reg_usb_cfg_speed_len 1 +#define reg_usb_cfg_speed_lsb 0 +#define xd_p_reg_usb_cfg_utmi16 ( 0xDD00) +#define p_reg_usb_cfg_utmi16 0xDD00 +#define reg_usb_cfg_utmi16_pos 1 +#define reg_usb_cfg_utmi16_len 1 +#define reg_usb_cfg_utmi16_lsb 0 +#define xd_p_reg_usb_cfg_test ( 0xDD00) +#define p_reg_usb_cfg_test 0xDD00 +#define reg_usb_cfg_test_pos 3 +#define reg_usb_cfg_test_len 3 +#define reg_usb_cfg_test_lsb 0 +#define xd_p_reg_usb_port_sim_reset ( 0xDD00) +#define p_reg_usb_port_sim_reset 0xDD00 +#define reg_usb_port_sim_reset_pos 6 +#define reg_usb_port_sim_reset_len 1 +#define reg_usb_port_sim_reset_lsb 0 +#define xd_p_reg_usb_port_run ( 0xDD00) +#define p_reg_usb_port_run 0xDD00 +#define reg_usb_port_run_pos 7 +#define reg_usb_port_run_len 1 +#define reg_usb_port_run_lsb 0 +#define xd_r_usb_line_state_0 ( 0xDD01) +#define r_usb_line_state_0 0xDD01 +#define usb_line_state_0_pos 0 +#define usb_line_state_0_len 1 +#define usb_line_state_0_lsb 0 +#define xd_r_usb_line_state_1 ( 0xDD01) +#define r_usb_line_state_1 0xDD01 +#define usb_line_state_1_pos 1 +#define usb_line_state_1_len 1 +#define usb_line_state_1_lsb 0 +#define xd_r_reg_usb_status_speed ( 0xDD01) +#define r_reg_usb_status_speed 0xDD01 +#define reg_usb_status_speed_pos 2 +#define reg_usb_status_speed_len 1 +#define reg_usb_status_speed_lsb 0 +#define xd_r_reg_usb_status_connect ( 0xDD01) +#define r_reg_usb_status_connect 0xDD01 +#define reg_usb_status_connect_pos 3 +#define reg_usb_status_connect_len 1 +#define reg_usb_status_connect_lsb 0 +#define xd_r_reg_usb_rx_buf ( 0xDD01) +#define r_reg_usb_rx_buf 0xDD01 +#define reg_usb_rx_buf_pos 4 +#define reg_usb_rx_buf_len 1 +#define reg_usb_rx_buf_lsb 0 +#define xd_r_reg_usb_port_reset ( 0xDD01) +#define r_reg_usb_port_reset 0xDD01 +#define reg_usb_port_reset_pos 5 +#define reg_usb_port_reset_len 1 +#define reg_usb_port_reset_lsb 0 +#define xd_r_reg_usb_port_suspend ( 0xDD01) +#define r_reg_usb_port_suspend 0xDD01 +#define reg_usb_port_suspend_pos 6 +#define reg_usb_port_suspend_len 1 +#define reg_usb_port_suspend_lsb 0 +#define xd_p_reg_ep1_tx_type ( 0xDD07) +#define p_reg_ep1_tx_type 0xDD07 +#define reg_ep1_tx_type_pos 2 +#define reg_ep1_tx_type_len 1 +#define reg_ep1_tx_type_lsb 0 +#define xd_p_reg_ep2_rx_type ( 0xDD07) +#define p_reg_ep2_rx_type 0xDD07 +#define reg_ep2_rx_type_pos 3 +#define reg_ep2_rx_type_len 1 +#define reg_ep2_rx_type_lsb 0 +#define xd_p_reg_ep3_tx_type ( 0xDD07) +#define p_reg_ep3_tx_type 0xDD07 +#define reg_ep3_tx_type_pos 4 +#define reg_ep3_tx_type_len 1 +#define reg_ep3_tx_type_lsb 0 +#define xd_p_reg_ep4_tx_type ( 0xDD07) +#define p_reg_ep4_tx_type 0xDD07 +#define reg_ep4_tx_type_pos 5 +#define reg_ep4_tx_type_len 1 +#define reg_ep4_tx_type_lsb 0 +#define xd_p_reg_ep5_tx_type ( 0xDD07) +#define p_reg_ep5_tx_type 0xDD07 +#define reg_ep5_tx_type_pos 6 +#define reg_ep5_tx_type_len 1 +#define reg_ep5_tx_type_lsb 0 +#define xd_p_reg_ep0_max_pkt ( 0xDD08) +#define p_reg_ep0_max_pkt 0xDD08 +#define reg_ep0_max_pkt_pos 0 +#define reg_ep0_max_pkt_len 8 +#define reg_ep0_max_pkt_lsb 0 +#define xd_p_reg_ep2_max_pkt ( 0xDD0A) +#define p_reg_ep2_max_pkt 0xDD0A +#define reg_ep2_max_pkt_pos 0 +#define reg_ep2_max_pkt_len 8 +#define reg_ep2_max_pkt_lsb 0 +#define xd_p_reg_ep4_max_pkt ( 0xDD0C) +#define p_reg_ep4_max_pkt 0xDD0C +#define reg_ep4_max_pkt_pos 0 +#define reg_ep4_max_pkt_len 8 +#define reg_ep4_max_pkt_lsb 0 +#define xd_p_reg_ep5_max_pkt ( 0xDD0D) +#define p_reg_ep5_max_pkt 0xDD0D +#define reg_ep5_max_pkt_pos 0 +#define reg_ep5_max_pkt_len 8 +#define reg_ep5_max_pkt_lsb 0 +#define xd_p_reg_usb_addr ( 0xDD10) +#define p_reg_usb_addr 0xDD10 +#define reg_usb_addr_pos 0 +#define reg_usb_addr_len 7 +#define reg_usb_addr_lsb 0 +#define xd_p_reg_usb_addr_now ( 0xDD10) +#define p_reg_usb_addr_now 0xDD10 +#define reg_usb_addr_now_pos 7 +#define reg_usb_addr_now_len 1 +#define reg_usb_addr_now_lsb 0 +#define xd_p_reg_ep0_tx_en ( 0xDD11) +#define p_reg_ep0_tx_en 0xDD11 +#define reg_ep0_tx_en_pos 0 +#define reg_ep0_tx_en_len 1 +#define reg_ep0_tx_en_lsb 0 +#define xd_p_reg_ep0_rx_en ( 0xDD11) +#define p_reg_ep0_rx_en 0xDD11 +#define reg_ep0_rx_en_pos 1 +#define reg_ep0_rx_en_len 1 +#define reg_ep0_rx_en_lsb 0 +#define xd_p_reg_ep1_tx_en ( 0xDD11) +#define p_reg_ep1_tx_en 0xDD11 +#define reg_ep1_tx_en_pos 2 +#define reg_ep1_tx_en_len 1 +#define reg_ep1_tx_en_lsb 0 +#define xd_p_reg_ep2_rx_en ( 0xDD11) +#define p_reg_ep2_rx_en 0xDD11 +#define reg_ep2_rx_en_pos 3 +#define reg_ep2_rx_en_len 1 +#define reg_ep2_rx_en_lsb 0 +#define xd_p_reg_ep3_tx_en ( 0xDD11) +#define p_reg_ep3_tx_en 0xDD11 +#define reg_ep3_tx_en_pos 4 +#define reg_ep3_tx_en_len 1 +#define reg_ep3_tx_en_lsb 0 +#define xd_p_reg_ep4_tx_en ( 0xDD11) +#define p_reg_ep4_tx_en 0xDD11 +#define reg_ep4_tx_en_pos 5 +#define reg_ep4_tx_en_len 1 +#define reg_ep4_tx_en_lsb 0 +#define xd_p_reg_ep5_tx_en ( 0xDD11) +#define p_reg_ep5_tx_en 0xDD11 +#define reg_ep5_tx_en_pos 6 +#define reg_ep5_tx_en_len 1 +#define reg_ep5_tx_en_lsb 0 +#define xd_p_reg_ep0_tx_stall ( 0xDD12) +#define p_reg_ep0_tx_stall 0xDD12 +#define reg_ep0_tx_stall_pos 0 +#define reg_ep0_tx_stall_len 1 +#define reg_ep0_tx_stall_lsb 0 +#define xd_p_reg_ep0_rx_stall ( 0xDD12) +#define p_reg_ep0_rx_stall 0xDD12 +#define reg_ep0_rx_stall_pos 1 +#define reg_ep0_rx_stall_len 1 +#define reg_ep0_rx_stall_lsb 0 +#define xd_p_reg_ep1_tx_stall ( 0xDD12) +#define p_reg_ep1_tx_stall 0xDD12 +#define reg_ep1_tx_stall_pos 2 +#define reg_ep1_tx_stall_len 1 +#define reg_ep1_tx_stall_lsb 0 +#define xd_p_reg_ep2_rx_stall ( 0xDD12) +#define p_reg_ep2_rx_stall 0xDD12 +#define reg_ep2_rx_stall_pos 3 +#define reg_ep2_rx_stall_len 1 +#define reg_ep2_rx_stall_lsb 0 +#define xd_p_reg_ep3_tx_stall ( 0xDD12) +#define p_reg_ep3_tx_stall 0xDD12 +#define reg_ep3_tx_stall_pos 4 +#define reg_ep3_tx_stall_len 1 +#define reg_ep3_tx_stall_lsb 0 +#define xd_p_reg_ep4_tx_stall ( 0xDD12) +#define p_reg_ep4_tx_stall 0xDD12 +#define reg_ep4_tx_stall_pos 5 +#define reg_ep4_tx_stall_len 1 +#define reg_ep4_tx_stall_lsb 0 +#define xd_p_reg_ep5_tx_stall ( 0xDD12) +#define p_reg_ep5_tx_stall 0xDD12 +#define reg_ep5_tx_stall_pos 6 +#define reg_ep5_tx_stall_len 1 +#define reg_ep5_tx_stall_lsb 0 +#define xd_p_reg_ep0_tx_nak ( 0xDD13) +#define p_reg_ep0_tx_nak 0xDD13 +#define reg_ep0_tx_nak_pos 0 +#define reg_ep0_tx_nak_len 1 +#define reg_ep0_tx_nak_lsb 0 +#define xd_p_reg_ep0_rx_nak ( 0xDD13) +#define p_reg_ep0_rx_nak 0xDD13 +#define reg_ep0_rx_nak_pos 1 +#define reg_ep0_rx_nak_len 1 +#define reg_ep0_rx_nak_lsb 0 +#define xd_p_reg_ep1_tx_nak ( 0xDD13) +#define p_reg_ep1_tx_nak 0xDD13 +#define reg_ep1_tx_nak_pos 2 +#define reg_ep1_tx_nak_len 1 +#define reg_ep1_tx_nak_lsb 0 +#define xd_p_reg_ep2_rx_nak ( 0xDD13) +#define p_reg_ep2_rx_nak 0xDD13 +#define reg_ep2_rx_nak_pos 3 +#define reg_ep2_rx_nak_len 1 +#define reg_ep2_rx_nak_lsb 0 +#define xd_p_reg_ep3_tx_nak ( 0xDD13) +#define p_reg_ep3_tx_nak 0xDD13 +#define reg_ep3_tx_nak_pos 4 +#define reg_ep3_tx_nak_len 1 +#define reg_ep3_tx_nak_lsb 0 +#define xd_p_reg_ep4_tx_nak ( 0xDD13) +#define p_reg_ep4_tx_nak 0xDD13 +#define reg_ep4_tx_nak_pos 5 +#define reg_ep4_tx_nak_len 1 +#define reg_ep4_tx_nak_lsb 0 +#define xd_p_reg_ep5_tx_nak ( 0xDD13) +#define p_reg_ep5_tx_nak 0xDD13 +#define reg_ep5_tx_nak_pos 6 +#define reg_ep5_tx_nak_len 1 +#define reg_ep5_tx_nak_lsb 0 +#define xd_p_reg_ep0_tx_nak_int_en ( 0xDD14) +#define p_reg_ep0_tx_nak_int_en 0xDD14 +#define reg_ep0_tx_nak_int_en_pos 0 +#define reg_ep0_tx_nak_int_en_len 1 +#define reg_ep0_tx_nak_int_en_lsb 0 +#define xd_p_reg_ep0_rx_nak_int_en ( 0xDD14) +#define p_reg_ep0_rx_nak_int_en 0xDD14 +#define reg_ep0_rx_nak_int_en_pos 1 +#define reg_ep0_rx_nak_int_en_len 1 +#define reg_ep0_rx_nak_int_en_lsb 0 +#define xd_p_reg_ep1_tx_nak_int_en ( 0xDD14) +#define p_reg_ep1_tx_nak_int_en 0xDD14 +#define reg_ep1_tx_nak_int_en_pos 2 +#define reg_ep1_tx_nak_int_en_len 1 +#define reg_ep1_tx_nak_int_en_lsb 0 +#define xd_p_reg_ep2_rx_nak_int_en ( 0xDD14) +#define p_reg_ep2_rx_nak_int_en 0xDD14 +#define reg_ep2_rx_nak_int_en_pos 3 +#define reg_ep2_rx_nak_int_en_len 1 +#define reg_ep2_rx_nak_int_en_lsb 0 +#define xd_p_reg_ep3_tx_nak_int_en ( 0xDD14) +#define p_reg_ep3_tx_nak_int_en 0xDD14 +#define reg_ep3_tx_nak_int_en_pos 4 +#define reg_ep3_tx_nak_int_en_len 1 +#define reg_ep3_tx_nak_int_en_lsb 0 +#define xd_p_reg_ep4_tx_nak_int_en ( 0xDD14) +#define p_reg_ep4_tx_nak_int_en 0xDD14 +#define reg_ep4_tx_nak_int_en_pos 5 +#define reg_ep4_tx_nak_int_en_len 1 +#define reg_ep4_tx_nak_int_en_lsb 0 +#define xd_p_reg_ep5_tx_nak_int_en ( 0xDD14) +#define p_reg_ep5_tx_nak_int_en 0xDD14 +#define reg_ep5_tx_nak_int_en_pos 6 +#define reg_ep5_tx_nak_int_en_len 1 +#define reg_ep5_tx_nak_int_en_lsb 0 +#define xd_p_reg_ep0_tx_done_int_en ( 0xDD15) +#define p_reg_ep0_tx_done_int_en 0xDD15 +#define reg_ep0_tx_done_int_en_pos 0 +#define reg_ep0_tx_done_int_en_len 1 +#define reg_ep0_tx_done_int_en_lsb 0 +#define xd_p_reg_ep0_rx_done_int_en ( 0xDD15) +#define p_reg_ep0_rx_done_int_en 0xDD15 +#define reg_ep0_rx_done_int_en_pos 1 +#define reg_ep0_rx_done_int_en_len 1 +#define reg_ep0_rx_done_int_en_lsb 0 +#define xd_p_reg_ep1_tx_done_int_en ( 0xDD15) +#define p_reg_ep1_tx_done_int_en 0xDD15 +#define reg_ep1_tx_done_int_en_pos 2 +#define reg_ep1_tx_done_int_en_len 1 +#define reg_ep1_tx_done_int_en_lsb 0 +#define xd_p_reg_ep2_rx_done_int_en ( 0xDD15) +#define p_reg_ep2_rx_done_int_en 0xDD15 +#define reg_ep2_rx_done_int_en_pos 3 +#define reg_ep2_rx_done_int_en_len 1 +#define reg_ep2_rx_done_int_en_lsb 0 +#define xd_p_reg_ep3_tx_done_int_en ( 0xDD15) +#define p_reg_ep3_tx_done_int_en 0xDD15 +#define reg_ep3_tx_done_int_en_pos 4 +#define reg_ep3_tx_done_int_en_len 1 +#define reg_ep3_tx_done_int_en_lsb 0 +#define xd_p_reg_ep4_tx_done_int_en ( 0xDD15) +#define p_reg_ep4_tx_done_int_en 0xDD15 +#define reg_ep4_tx_done_int_en_pos 5 +#define reg_ep4_tx_done_int_en_len 1 +#define reg_ep4_tx_done_int_en_lsb 0 +#define xd_p_reg_ep5_tx_done_int_en ( 0xDD15) +#define p_reg_ep5_tx_done_int_en 0xDD15 +#define reg_ep5_tx_done_int_en_pos 6 +#define reg_ep5_tx_done_int_en_len 1 +#define reg_ep5_tx_done_int_en_lsb 0 +#define xd_p_reg_ep0_tx_fail_int_en ( 0xDD16) +#define p_reg_ep0_tx_fail_int_en 0xDD16 +#define reg_ep0_tx_fail_int_en_pos 0 +#define reg_ep0_tx_fail_int_en_len 1 +#define reg_ep0_tx_fail_int_en_lsb 0 +#define xd_p_reg_ep0_rx_fail_int_en ( 0xDD16) +#define p_reg_ep0_rx_fail_int_en 0xDD16 +#define reg_ep0_rx_fail_int_en_pos 1 +#define reg_ep0_rx_fail_int_en_len 1 +#define reg_ep0_rx_fail_int_en_lsb 0 +#define xd_p_reg_ep1_tx_fail_int_en ( 0xDD16) +#define p_reg_ep1_tx_fail_int_en 0xDD16 +#define reg_ep1_tx_fail_int_en_pos 2 +#define reg_ep1_tx_fail_int_en_len 1 +#define reg_ep1_tx_fail_int_en_lsb 0 +#define xd_p_reg_ep2_rx_fail_int_en ( 0xDD16) +#define p_reg_ep2_rx_fail_int_en 0xDD16 +#define reg_ep2_rx_fail_int_en_pos 3 +#define reg_ep2_rx_fail_int_en_len 1 +#define reg_ep2_rx_fail_int_en_lsb 0 +#define xd_p_reg_ep3_tx_fail_int_en ( 0xDD16) +#define p_reg_ep3_tx_fail_int_en 0xDD16 +#define reg_ep3_tx_fail_int_en_pos 4 +#define reg_ep3_tx_fail_int_en_len 1 +#define reg_ep3_tx_fail_int_en_lsb 0 +#define xd_p_reg_ep4_tx_fail_int_en ( 0xDD16) +#define p_reg_ep4_tx_fail_int_en 0xDD16 +#define reg_ep4_tx_fail_int_en_pos 5 +#define reg_ep4_tx_fail_int_en_len 1 +#define reg_ep4_tx_fail_int_en_lsb 0 +#define xd_p_reg_ep5_tx_fail_int_en ( 0xDD16) +#define p_reg_ep5_tx_fail_int_en 0xDD16 +#define reg_ep5_tx_fail_int_en_pos 6 +#define reg_ep5_tx_fail_int_en_len 1 +#define reg_ep5_tx_fail_int_en_lsb 0 +#define xd_p_reg_suspend_int_en ( 0xDD17) +#define p_reg_suspend_int_en 0xDD17 +#define reg_suspend_int_en_pos 0 +#define reg_suspend_int_en_len 1 +#define reg_suspend_int_en_lsb 0 +#define xd_p_reg_bus_reset_int_en ( 0xDD17) +#define p_reg_bus_reset_int_en 0xDD17 +#define reg_bus_reset_int_en_pos 1 +#define reg_bus_reset_int_en_len 1 +#define reg_bus_reset_int_en_lsb 0 +#define xd_p_reg_ep0_setup_int_en ( 0xDD17) +#define p_reg_ep0_setup_int_en 0xDD17 +#define reg_ep0_setup_int_en_pos 2 +#define reg_ep0_setup_int_en_len 1 +#define reg_ep0_setup_int_en_lsb 0 +#define xd_p_reg_ep0_tx_nak_int ( 0xDD18) +#define p_reg_ep0_tx_nak_int 0xDD18 +#define reg_ep0_tx_nak_int_pos 0 +#define reg_ep0_tx_nak_int_len 1 +#define reg_ep0_tx_nak_int_lsb 0 +#define xd_p_reg_ep0_rx_nak_int ( 0xDD18) +#define p_reg_ep0_rx_nak_int 0xDD18 +#define reg_ep0_rx_nak_int_pos 1 +#define reg_ep0_rx_nak_int_len 1 +#define reg_ep0_rx_nak_int_lsb 0 +#define xd_p_reg_ep1_tx_nak_int ( 0xDD18) +#define p_reg_ep1_tx_nak_int 0xDD18 +#define reg_ep1_tx_nak_int_pos 2 +#define reg_ep1_tx_nak_int_len 1 +#define reg_ep1_tx_nak_int_lsb 0 +#define xd_p_reg_ep2_rx_nak_int ( 0xDD18) +#define p_reg_ep2_rx_nak_int 0xDD18 +#define reg_ep2_rx_nak_int_pos 3 +#define reg_ep2_rx_nak_int_len 1 +#define reg_ep2_rx_nak_int_lsb 0 +#define xd_p_reg_ep3_tx_nak_int ( 0xDD18) +#define p_reg_ep3_tx_nak_int 0xDD18 +#define reg_ep3_tx_nak_int_pos 4 +#define reg_ep3_tx_nak_int_len 1 +#define reg_ep3_tx_nak_int_lsb 0 +#define xd_p_reg_ep4_tx_nak_int ( 0xDD18) +#define p_reg_ep4_tx_nak_int 0xDD18 +#define reg_ep4_tx_nak_int_pos 5 +#define reg_ep4_tx_nak_int_len 1 +#define reg_ep4_tx_nak_int_lsb 0 +#define xd_p_reg_ep5_tx_nak_int ( 0xDD18) +#define p_reg_ep5_tx_nak_int 0xDD18 +#define reg_ep5_tx_nak_int_pos 6 +#define reg_ep5_tx_nak_int_len 1 +#define reg_ep5_tx_nak_int_lsb 0 +#define xd_p_reg_ep0_tx_done_int ( 0xDD19) +#define p_reg_ep0_tx_done_int 0xDD19 +#define reg_ep0_tx_done_int_pos 0 +#define reg_ep0_tx_done_int_len 1 +#define reg_ep0_tx_done_int_lsb 0 +#define xd_p_reg_ep0_rx_done_int ( 0xDD19) +#define p_reg_ep0_rx_done_int 0xDD19 +#define reg_ep0_rx_done_int_pos 1 +#define reg_ep0_rx_done_int_len 1 +#define reg_ep0_rx_done_int_lsb 0 +#define xd_p_reg_ep1_tx_done_int ( 0xDD19) +#define p_reg_ep1_tx_done_int 0xDD19 +#define reg_ep1_tx_done_int_pos 2 +#define reg_ep1_tx_done_int_len 1 +#define reg_ep1_tx_done_int_lsb 0 +#define xd_p_reg_ep2_rx_done_int ( 0xDD19) +#define p_reg_ep2_rx_done_int 0xDD19 +#define reg_ep2_rx_done_int_pos 3 +#define reg_ep2_rx_done_int_len 1 +#define reg_ep2_rx_done_int_lsb 0 +#define xd_p_reg_ep3_tx_done_int ( 0xDD19) +#define p_reg_ep3_tx_done_int 0xDD19 +#define reg_ep3_tx_done_int_pos 4 +#define reg_ep3_tx_done_int_len 1 +#define reg_ep3_tx_done_int_lsb 0 +#define xd_p_reg_ep4_tx_done_int ( 0xDD19) +#define p_reg_ep4_tx_done_int 0xDD19 +#define reg_ep4_tx_done_int_pos 5 +#define reg_ep4_tx_done_int_len 1 +#define reg_ep4_tx_done_int_lsb 0 +#define xd_p_reg_ep5_tx_done_int ( 0xDD19) +#define p_reg_ep5_tx_done_int 0xDD19 +#define reg_ep5_tx_done_int_pos 6 +#define reg_ep5_tx_done_int_len 1 +#define reg_ep5_tx_done_int_lsb 0 +#define xd_p_reg_ep0_tx_fail_int ( 0xDD1A) +#define p_reg_ep0_tx_fail_int 0xDD1A +#define reg_ep0_tx_fail_int_pos 0 +#define reg_ep0_tx_fail_int_len 1 +#define reg_ep0_tx_fail_int_lsb 0 +#define xd_p_reg_ep0_rx_fail_int ( 0xDD1A) +#define p_reg_ep0_rx_fail_int 0xDD1A +#define reg_ep0_rx_fail_int_pos 1 +#define reg_ep0_rx_fail_int_len 1 +#define reg_ep0_rx_fail_int_lsb 0 +#define xd_p_reg_ep1_tx_fail_int ( 0xDD1A) +#define p_reg_ep1_tx_fail_int 0xDD1A +#define reg_ep1_tx_fail_int_pos 2 +#define reg_ep1_tx_fail_int_len 1 +#define reg_ep1_tx_fail_int_lsb 0 +#define xd_p_reg_ep2_rx_fail_int ( 0xDD1A) +#define p_reg_ep2_rx_fail_int 0xDD1A +#define reg_ep2_rx_fail_int_pos 3 +#define reg_ep2_rx_fail_int_len 1 +#define reg_ep2_rx_fail_int_lsb 0 +#define xd_p_reg_ep3_tx_fail_int ( 0xDD1A) +#define p_reg_ep3_tx_fail_int 0xDD1A +#define reg_ep3_tx_fail_int_pos 4 +#define reg_ep3_tx_fail_int_len 1 +#define reg_ep3_tx_fail_int_lsb 0 +#define xd_p_reg_ep4_tx_fail_int ( 0xDD1A) +#define p_reg_ep4_tx_fail_int 0xDD1A +#define reg_ep4_tx_fail_int_pos 5 +#define reg_ep4_tx_fail_int_len 1 +#define reg_ep4_tx_fail_int_lsb 0 +#define xd_p_reg_ep5_tx_fail_int ( 0xDD1A) +#define p_reg_ep5_tx_fail_int 0xDD1A +#define reg_ep5_tx_fail_int_pos 6 +#define reg_ep5_tx_fail_int_len 1 +#define reg_ep5_tx_fail_int_lsb 0 +#define xd_p_reg_suspend_int ( 0xDD1B) +#define p_reg_suspend_int 0xDD1B +#define reg_suspend_int_pos 0 +#define reg_suspend_int_len 1 +#define reg_suspend_int_lsb 0 +#define xd_p_reg_bus_reset_int ( 0xDD1B) +#define p_reg_bus_reset_int 0xDD1B +#define reg_bus_reset_int_pos 1 +#define reg_bus_reset_int_len 1 +#define reg_bus_reset_int_lsb 0 +#define xd_p_reg_ep0_setup_int ( 0xDD1B) +#define p_reg_ep0_setup_int 0xDD1B +#define reg_ep0_setup_int_pos 2 +#define reg_ep0_setup_int_len 1 +#define reg_ep0_setup_int_lsb 0 +#define xd_r_usbc_int ( 0xDD1B) +#define r_usbc_int 0xDD1B +#define usbc_int_pos 3 +#define usbc_int_len 1 +#define usbc_int_lsb 0 +#define xd_r_usb_ir_int ( 0xDD1B) +#define r_usb_ir_int 0xDD1B +#define usb_ir_int_pos 4 +#define usb_ir_int_len 1 +#define usb_ir_int_lsb 0 +#define xd_p_reg_ep0_tx_rst ( 0xDD1D) +#define p_reg_ep0_tx_rst 0xDD1D +#define reg_ep0_tx_rst_pos 0 +#define reg_ep0_tx_rst_len 1 +#define reg_ep0_tx_rst_lsb 0 +#define xd_p_reg_ep0_rx_rst ( 0xDD1D) +#define p_reg_ep0_rx_rst 0xDD1D +#define reg_ep0_rx_rst_pos 1 +#define reg_ep0_rx_rst_len 1 +#define reg_ep0_rx_rst_lsb 0 +#define xd_p_reg_ep1_tx_rst ( 0xDD1D) +#define p_reg_ep1_tx_rst 0xDD1D +#define reg_ep1_tx_rst_pos 2 +#define reg_ep1_tx_rst_len 1 +#define reg_ep1_tx_rst_lsb 0 +#define xd_p_reg_ep2_rx_rst ( 0xDD1D) +#define p_reg_ep2_rx_rst 0xDD1D +#define reg_ep2_rx_rst_pos 3 +#define reg_ep2_rx_rst_len 1 +#define reg_ep2_rx_rst_lsb 0 +#define xd_p_reg_ep3_tx_rst ( 0xDD1D) +#define p_reg_ep3_tx_rst 0xDD1D +#define reg_ep3_tx_rst_pos 4 +#define reg_ep3_tx_rst_len 1 +#define reg_ep3_tx_rst_lsb 0 +#define xd_p_reg_ep4_tx_rst ( 0xDD1D) +#define p_reg_ep4_tx_rst 0xDD1D +#define reg_ep4_tx_rst_pos 5 +#define reg_ep4_tx_rst_len 1 +#define reg_ep4_tx_rst_lsb 0 +#define xd_p_reg_ep5_tx_rst ( 0xDD1D) +#define p_reg_ep5_tx_rst 0xDD1D +#define reg_ep5_tx_rst_pos 6 +#define reg_ep5_tx_rst_len 1 +#define reg_ep5_tx_rst_lsb 0 +#define xd_r_reg_ep0_tx_active ( 0xDD1E) +#define r_reg_ep0_tx_active 0xDD1E +#define reg_ep0_tx_active_pos 0 +#define reg_ep0_tx_active_len 1 +#define reg_ep0_tx_active_lsb 0 +#define xd_r_reg_ep0_rx_active ( 0xDD1E) +#define r_reg_ep0_rx_active 0xDD1E +#define reg_ep0_rx_active_pos 1 +#define reg_ep0_rx_active_len 1 +#define reg_ep0_rx_active_lsb 0 +#define xd_r_reg_ep1_tx_active ( 0xDD1E) +#define r_reg_ep1_tx_active 0xDD1E +#define reg_ep1_tx_active_pos 2 +#define reg_ep1_tx_active_len 1 +#define reg_ep1_tx_active_lsb 0 +#define xd_r_reg_ep2_rx_active ( 0xDD1E) +#define r_reg_ep2_rx_active 0xDD1E +#define reg_ep2_rx_active_pos 3 +#define reg_ep2_rx_active_len 1 +#define reg_ep2_rx_active_lsb 0 +#define xd_r_reg_ep3_tx_active ( 0xDD1E) +#define r_reg_ep3_tx_active 0xDD1E +#define reg_ep3_tx_active_pos 4 +#define reg_ep3_tx_active_len 1 +#define reg_ep3_tx_active_lsb 0 +#define xd_r_reg_ep4_tx_active ( 0xDD1E) +#define r_reg_ep4_tx_active 0xDD1E +#define reg_ep4_tx_active_pos 5 +#define reg_ep4_tx_active_len 1 +#define reg_ep4_tx_active_lsb 0 +#define xd_r_reg_ep5_tx_active ( 0xDD1E) +#define r_reg_ep5_tx_active 0xDD1E +#define reg_ep5_tx_active_pos 6 +#define reg_ep5_tx_active_len 1 +#define reg_ep5_tx_active_lsb 0 +#define xd_p_reg_usb_setup_reset ( 0xDD1F) +#define p_reg_usb_setup_reset 0xDD1F +#define reg_usb_setup_reset_pos 0 +#define reg_usb_setup_reset_len 1 +#define reg_usb_setup_reset_lsb 0 +#define xd_p_reg_usb_ep4_retry_new ( 0xDD1F) +#define p_reg_usb_ep4_retry_new 0xDD1F +#define reg_usb_ep4_retry_new_pos 1 +#define reg_usb_ep4_retry_new_len 1 +#define reg_usb_ep4_retry_new_lsb 0 +#define xd_p_reg_usb_ep5_retry_new ( 0xDD1F) +#define p_reg_usb_ep5_retry_new 0xDD1F +#define reg_usb_ep5_retry_new_pos 2 +#define reg_usb_ep5_retry_new_len 1 +#define reg_usb_ep5_retry_new_lsb 0 |