diff options
| author | Wilrik de Loose <wilrik@wilrik.nl> | 2008-05-14 10:28:57 (GMT) |
|---|---|---|
| committer | Wilrik de Loose <wilrik@wilrik.nl> | 2008-05-14 10:28:57 (GMT) |
| commit | 8338135af544bfa284a7cc45affc06ee6079f8c5 (patch) | |
| tree | 2295a1710628482e97e305ce5a6bdebda567bb62 /report/chapter6.tex | |
| parent | 5620af5abcd7e4eb5e123603a497a407032f2107 (diff) | |
| download | 2in25-8338135af544bfa284a7cc45affc06ee6079f8c5.zip 2in25-8338135af544bfa284a7cc45affc06ee6079f8c5.tar.gz 2in25-8338135af544bfa284a7cc45affc06ee6079f8c5.tar.bz2 | |
Added the work of Joshus to the report + the part about processors (pipelined/general purpose)
Diffstat (limited to 'report/chapter6.tex')
| -rw-r--r-- | report/chapter6.tex | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/report/chapter6.tex b/report/chapter6.tex new file mode 100644 index 0000000..52b9773 --- /dev/null +++ b/report/chapter6.tex @@ -0,0 +1,22 @@ +\section{Literature}
+
+\small
+
+\begin{tabbing}
+
+\textbf{[2]} \= Jonathan Simonson, Janak H. Patel. Use of preferred preemption points in cache-based \\
+\> real-time systems. IEEE Computer Society Washington, DC, USA 1995 \\
+
+\\
+
+\textbf{[2]} \= Healy, C.A., Whalley, D.B., Harmon, M.G. Integrating the Timing Analysis of Pipelining \\
+\> and Instruction Caching. Dept. of Comput. Sci., Florida State Univ., Tallahassee, FL 1995 \\
+
+\\
+
+\textbf{[3]} \= Jonathan Simonson, Janak H. Patel. Use of preferred preemption points in cache-based \\
+\> real-time systems. IEEE Computer Society Washington, DC, USA 1995 \\
+
+\\
+
+\end{tabbing}
|